#
# Copyright (c) Hisilicon Technologies Co., Ltd. 2021-2021. All rights reserved.
#

INCLUDE_DIR += \
	-I$(HVGR_PATH)/pm \
	-I$(HVGR_PATH)/pm/power \
	-I$(HVGR_PATH)/pm/dfx \
	-I$(HVGR_PATH)/pm/dvfs \
	-I$(HVGR_PATH)/pm/driver \
	-I$(HVGR_PATH)/pm/driver/$(CHIP_VER_DIR)

SRC += \
	$(HVGR_ROOT)/pm/hvgr_pm.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_core_mask.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_policy.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_power.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_sr.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_state_machine.c \
	$(HVGR_ROOT)/pm/power/hvgr_pm_gpu_reset.c \
	$(HVGR_ROOT)/pm/driver/hvgr_pm_driver_base.c \
	$(HVGR_ROOT)/pm/dvfs/hvgr_pm_dvfs.c \
	$(HVGR_ROOT)/pm/dfx/hvgr_pm_dfx.c \
	$(HVGR_ROOT)/pm/driver/$(CHIP_VER_DIR)/hvgr_pm_driver_adapt.c

# V350 support fastpower
ifeq ($(HVGR_FAST_PWR), 1)
INCLUDE_DIR += \
	-I$(HVGR_PATH)/pm/power/fast_power

SRC += \
	$(HVGR_ROOT)/pm/power/fast_power/hvgr_pm_fast_power.c
endif

# V500 support rtu indie power
ifeq ($(HVGR_RTU_PWR), 1)
INCLUDE_DIR += \
	-I$(HVGR_PATH)/pm/power/rtu_power

SRC += \
	$(HVGR_ROOT)/pm/power/rtu_power/hvgr_pm_rtu_power.c
endif

ifeq ($(CONFIG_GPU_VIRTUAL_DEVFREQ), y)
    INCLUDE_DIR += \
        -I$(HVGR_PATH)/pm/virtual_devfreq
    SRC += \
        $(HVGR_ROOT)/pm/virtual_devfreq/hvgr_virtual_devfreq.c
endif

DEFINES += -DHVGR_GPU_POWER_ASYNC