dev_jazz.cc Source File

Back to the index.

dev_jazz.cc
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2004-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Microsoft Jazz-related stuff (Acer PICA-61, etc)
29  *
30  * TODO/NOTE: This is mostly a quick hack, it doesn't really implement
31  * much of the Jazz architecture. Also, the a0/20 isa-like stuff is
32  * not supposed to be here.
33  *
34  * TODO: Figure out how the int enable mask works; it seems to be shifted
35  * 10 bits (?) according to NetBSD/arc sources.
36  *
37  * TODO: Don't hardcode the timer to 100 Hz.
38  *
39  * JAZZ interrupts 0..14 are connected to MIPS irq 3,
40  * JAZZ interrupt 15 (the timer) is connected to MIPS irq 6,
41  * and ISA interrupts 0..15 are connected to MIPS irq 4.
42  */
43 
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 
48 #include "cpu.h"
49 #include "device.h"
50 #include "devices.h"
51 #include "interrupt.h"
52 #include "machine.h"
53 #include "memory.h"
54 #include "misc.h"
55 #include "timer.h"
56 
58 #include "thirdparty/pica.h"
59 
60 
61 #define DEV_JAZZ_LENGTH 0x280
62 #define DEV_JAZZ_TICKSHIFT 14
63 #define PICA_TIMER_IRQ 15
64 
65 struct jazz_data {
69 
70  struct cpu *cpu;
71 
72  /* Jazz stuff: */
73  uint32_t int_enable_mask; /* TODO! */
74  uint32_t int_asserted;
75 
76  /* ISA stuff: */
78  uint32_t isa_int_asserted;
79 
80  int interval;
82 
83  struct timer *timer;
88 
91 
92  uint32_t dma0_mode;
93  uint32_t dma0_enable;
94  uint32_t dma0_count;
95  uint32_t dma0_addr;
96 
97  uint32_t dma1_mode;
98  /* same for dma1,2,3 actually (TODO) */
99 
100  int led;
101 };
102 
103 
105 {
108  else
110 }
111 
112 
114 {
115  struct jazz_data *d = (struct jazz_data *) interrupt->extra;
116  d->int_asserted |= (1 << interrupt->line);
117 
118  if (d->int_asserted & 0x7fff)
120  if (d->int_asserted & 0x8000)
122 }
124 {
125  struct jazz_data *d = (struct jazz_data *) interrupt->extra;
126  d->int_asserted &= ~(1 << interrupt->line);
127 
128  if (!(d->int_asserted & 0x7fff))
130  if (!(d->int_asserted & 0x8000))
132 }
134 {
135  struct jazz_data *d = (struct jazz_data *) interrupt->extra;
136  d->isa_int_asserted |= (1 << interrupt->line);
138 }
140 {
141  struct jazz_data *d = (struct jazz_data *) interrupt->extra;
142  d->isa_int_asserted &= ~(1 << interrupt->line);
144 }
145 
146 
147 /*
148  * dev_jazz_dma_controller():
149  */
150 size_t dev_jazz_dma_controller(void *dma_controller_data,
151  unsigned char *data, size_t len, int writeflag)
152 {
153  struct jazz_data *d = (struct jazz_data *) dma_controller_data;
154  struct cpu *cpu = d->cpu;
155  int i, enab_writeflag;
156  int res, ncpy;
157  uint32_t dma_addr;
158  unsigned char tr[sizeof(uint32_t)];
159  uint32_t phys_addr;
160 
161 #if 0
162  fatal("[ dev_jazz_dma_controller(): writeflag=%i, len=%i, data =",
163  writeflag, (int)len);
164  for (i=0; i<len; i++)
165  fatal(" %02x", data[i]);
166  fatal(" mode=%08x enable=%08x count=%08x addr=%08x",
167  d->dma0_mode, d->dma0_enable, d->dma0_count, d->dma0_addr);
168  fatal(" table=%08x",
170  fatal(" ]\n");
171 #endif
172 
173  if (!(d->dma0_enable & R4030_DMA_ENAB_RUN)) {
174  fatal("[ dev_jazz_dma_controller(): dma not enabled? ]\n");
175  /* return 0; */
176  }
177 
178  /* R4030 "write" means write to the device, writeflag as the
179  argument to this function means write to memory. */
180  enab_writeflag = (d->dma0_enable & R4030_DMA_ENAB_WRITE)? 0 : 1;
181  if (enab_writeflag != writeflag) {
182  fatal("[ dev_jazz_dma_controller(): wrong direction? ]\n");
183  return 0;
184  }
185 
186  dma_addr = d->dma0_addr;
187  i = 0;
188  while (dma_addr < d->dma0_addr + d->dma0_count && i < (int32_t)len) {
189 
190  res = cpu->memory_rw(cpu, cpu->mem,
191  d->dma_translation_table_base + (dma_addr >> 12) * 8,
192  tr, sizeof(tr), 0, PHYSICAL | NO_EXCEPTIONS);
193 
195  phys_addr = (tr[0] << 24) + (tr[1] << 16) +
196  (tr[2] << 8) + tr[3];
197  else
198  phys_addr = (tr[3] << 24) + (tr[2] << 16) +
199  (tr[1] << 8) + tr[0];
200  phys_addr &= ~0xfff; /* just in case */
201  phys_addr += (dma_addr & 0xfff);
202 
203  /* fatal(" !!! dma_addr = %08x, phys_addr = %08x\n",
204  (int)dma_addr, (int)phys_addr); */
205 
206  /* Speed up the copying by copying 16 or 256 bytes: */
207  ncpy = 1;
208  if ((phys_addr & 15) == 0 && i + 15 <= (int32_t)len)
209  ncpy = 15;
210  if ((phys_addr & 255) == 0 && i + 255 <= (int32_t)len)
211  ncpy = 255;
212 
213  res = cpu->memory_rw(cpu, cpu->mem, phys_addr,
214  &data[i], ncpy, writeflag, PHYSICAL | NO_EXCEPTIONS);
215 
216  dma_addr += ncpy;
217  i += ncpy;
218  }
219 
220  /* TODO: Is this correct? */
221  d->dma0_count = 0;
222 
223  return len;
224 }
225 
226 
227 static void timer_tick(struct timer *t, void *extra)
228 {
229  struct jazz_data *d = (struct jazz_data *) extra;
231 }
232 
233 
235 {
236  struct jazz_data *d = (struct jazz_data *) extra;
237 
238  /* Used by NetBSD/arc and OpenBSD/arc: */
239  if (d->interval_start > 0 && d->interval > 0
240  && (d->int_enable_mask & 2) /* Hm? */ ) {
241  d->interval -= 2;
242  if (d->interval <= 0) {
243  /* debug("[ jazz: interval timer interrupt ]\n");
244  INTERRUPT_ASSERT(d->jazz_timer_irq); */
245  }
246 
247  /* New timer system: */
248  if (d->pending_timer_interrupts > 0)
250  }
251 
252  /* Linux? */
253  if (d->jazz_timer_value != 0) {
254  d->jazz_timer_current -= 5;
255  if (d->jazz_timer_current < 1) {
257  /* INTERRUPT_ASSERT(d->mips_irq_6); */
258  }
259 
260  /* New timer system: */
261  if (d->pending_timer_interrupts > 0)
263  }
264 }
265 
266 
268 {
269  struct jazz_data *d = (struct jazz_data *) extra;
270  uint64_t idata = 0, odata = 0;
271  int regnr;
272 
273  if (writeflag == MEM_WRITE)
274  idata = memory_readmax64(cpu, data, len);
275 
276  regnr = relative_addr / sizeof(uint32_t);
277 
278  switch (relative_addr) {
279  case R4030_SYS_CONFIG:
280  if (writeflag == MEM_WRITE) {
281  fatal("[ jazz: unimplemented write to R4030_SYS_CONFIG"
282  ", data=0x%08x ]\n", (int)idata);
283  } else {
284  /* Reading the config register should give
285  0x0104 or 0x0410. Why? TODO */
286  odata = 0x104;
287  }
288  break;
289  case R4030_SYS_TL_BASE:
290  if (writeflag == MEM_WRITE) {
291  d->dma_translation_table_base = idata;
292  } else {
293  odata = d->dma_translation_table_base;
294  }
295  break;
296  case R4030_SYS_TL_LIMIT:
297  if (writeflag == MEM_WRITE) {
298  d->dma_translation_table_limit = idata;
299  } else {
300  odata = d->dma_translation_table_limit;
301  }
302  break;
303  case R4030_SYS_TL_IVALID:
304  /* TODO: Does invalidation actually need to be implemented? */
305  break;
306  case R4030_SYS_DMA0_REGS:
307  if (writeflag == MEM_WRITE) {
308  d->dma0_mode = idata;
309  } else {
310  odata = d->dma0_mode;
311  }
312  break;
313  case R4030_SYS_DMA0_REGS + 0x8:
314  if (writeflag == MEM_WRITE) {
315  d->dma0_enable = idata;
316  } else {
317  odata = d->dma0_enable;
318  }
319  break;
320  case R4030_SYS_DMA0_REGS + 0x10:
321  if (writeflag == MEM_WRITE) {
322  d->dma0_count = idata;
323  } else {
324  odata = d->dma0_count;
325  }
326  break;
327  case R4030_SYS_DMA0_REGS + 0x18:
328  if (writeflag == MEM_WRITE) {
329  d->dma0_addr = idata;
330  } else {
331  odata = d->dma0_addr;
332  }
333  break;
334  case R4030_SYS_DMA1_REGS:
335  if (writeflag == MEM_WRITE) {
336  d->dma1_mode = idata;
337  } else {
338  odata = d->dma1_mode;
339  }
340  break;
342  /* ? */
343 printf("R4030_SYS_ISA_VECTOR: w=%i\n", writeflag);
344  {
345  uint32_t x = d->isa_int_asserted
346  & d->isa_int_enable_mask;
347  odata = 0;
348  while (odata < 16) {
349  if (x & (1 << odata))
350  break;
351  odata ++;
352  }
353  if (odata >= 16)
354  odata = 0;
355  }
356  break;
357  case R4030_SYS_IT_VALUE: /* Interval timer reload value */
358  if (writeflag == MEM_WRITE) {
359  d->interval_start = idata;
360  d->interval = d->interval_start;
361  } else
362  odata = d->interval_start;
363  break;
364  case R4030_SYS_IT_STAT:
365  /* Accessing this word seems to acknowledge interrupts? */
367  if (d->pending_timer_interrupts > 0)
369 
370  if (writeflag == MEM_WRITE)
371  d->interval = idata;
372  else
373  odata = d->interval;
374  d->interval = d->interval_start;
375  break;
376  case R4030_SYS_EXT_IMASK:
377  if (writeflag == MEM_WRITE) {
378  int old_assert_3 = (0x7fff &
379  d->int_asserted & d->int_enable_mask);
380  int old_assert_6 = (0x8000 &
381  d->int_asserted & d->int_enable_mask);
382  int new_assert_3, new_assert_6;
383 
384  d->int_enable_mask = idata;
385 
386  new_assert_3 =
387  d->int_asserted & d->int_enable_mask & 0x7fff;
388  new_assert_6 =
389  d->int_asserted & d->int_enable_mask & 0x8000;
390 
391  if (old_assert_3 && !new_assert_3)
393  else if (!old_assert_3 && new_assert_3)
395 
396  if (old_assert_6 && !new_assert_6)
398  else if (!old_assert_6 && new_assert_6)
400  } else
401  odata = d->int_enable_mask;
402  break;
403  default:
404  if (writeflag == MEM_WRITE) {
405  fatal("[ jazz: unimplemented write to address 0x%x"
406  ", data=0x%02x ]\n", (int)relative_addr,
407  (int)idata);
408  } else {
409  fatal("[ jazz: unimplemented read from address 0x%x"
410  " ]\n", (int)relative_addr);
411  }
412  }
413 
414  if (writeflag == MEM_READ)
415  memory_writemax64(cpu, data, len, odata);
416 
417  return 1;
418 }
419 
420 
421 DEVICE_ACCESS(jazz_led)
422 {
423  struct jazz_data *d = (struct jazz_data *) extra;
424  uint64_t idata = 0, odata = 0;
425  int regnr;
426 
427  if (writeflag == MEM_WRITE)
428  idata = memory_readmax64(cpu, data, len);
429 
430  regnr = relative_addr / sizeof(uint32_t);
431 
432  switch (relative_addr) {
433  case 0:
434  if (writeflag == MEM_WRITE) {
435  d->led = idata;
436  debug("[ jazz_led: write to LED: 0x%02x ]\n",
437  (int)idata);
438  } else {
439  odata = d->led;
440  }
441  break;
442  default:
443  if (writeflag == MEM_WRITE) {
444  fatal("[ jazz_led: unimplemented write to address 0x%x"
445  ", data=0x%02x ]\n", (int)relative_addr,
446  (int)idata);
447  } else {
448  fatal("[ jazz_led: unimplemented read from address 0x%x"
449  " ]\n", (int)relative_addr);
450  }
451  }
452 
453  if (writeflag == MEM_READ)
454  memory_writemax64(cpu, data, len, odata);
455 
456  return 1;
457 }
458 
459 
460 /*
461  * dev_jazz_a0_access():
462  *
463  * ISA interrupt stuff, high 8 interrupts.
464  *
465  * TODO: use isa8 stuff instead!
466  */
468 {
469  struct jazz_data *d = (struct jazz_data *) extra;
470  uint64_t idata = 0, odata = 0;
471 
472  if (writeflag == MEM_WRITE)
473  idata = memory_readmax64(cpu, data, len);
474 
475  switch (relative_addr) {
476  case 0:
477  if (writeflag == MEM_WRITE) {
478  /* TODO: only if idata == 0x20? */
479  d->isa_int_asserted &= 0xff;
480 
482  }
483  break;
484  case 1:
485  if (writeflag == MEM_WRITE) {
486  idata = ((idata ^ 0xff) & 0xff) << 8;
488  (d->isa_int_enable_mask & 0xff) | idata;
489  debug("[ jazz_isa_a0: setting isa_int_enable_mask "
490  "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
491 
493  } else
494  odata = d->isa_int_enable_mask;
495  break;
496  default:
497  if (writeflag == MEM_WRITE) {
498  fatal("[ jazz_isa_a0: unimplemented write to "
499  "address 0x%x, data=0x%02x ]\n",
500  (int)relative_addr, (int)idata);
501  } else {
502  fatal("[ jazz_isa_a0: unimplemented read from "
503  "address 0x%x ]\n", (int)relative_addr);
504  }
505  }
506 
507  if (writeflag == MEM_READ)
508  memory_writemax64(cpu, data, len, odata);
509 
510  return 1;
511 }
512 
513 
514 /*
515  * dev_jazz_20_access():
516  *
517  * ISA interrupt stuff, low 8 interrupts.
518  */
520 {
521  struct jazz_data *d = (struct jazz_data *) extra;
522  uint64_t idata = 0, odata = 0;
523 
524  if (writeflag == MEM_WRITE)
525  idata = memory_readmax64(cpu, data, len);
526 
527  switch (relative_addr) {
528  case 0:
529  if (writeflag == MEM_WRITE) {
530  /* TODO: only if idata == 0x20? */
531  d->isa_int_asserted &= 0xff00;
533  }
534  break;
535  case 1:
536  if (writeflag == MEM_WRITE) {
537  idata = (idata ^ 0xff) & 0xff;
539  (d->isa_int_enable_mask & 0xff00) | idata;
540  debug("[ jazz_isa_20: setting isa_int_enable_mask "
541  "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
542 
544  } else
545  odata = d->isa_int_enable_mask;
546  break;
547  default:
548  if (writeflag == MEM_WRITE) {
549  fatal("[ jazz_isa_20: unimplemented write to "
550  "address 0x%x, data=0x%02x ]\n",
551  (int)relative_addr, (int)idata);
552  } else {
553  fatal("[ jazz_isa_20: unimplemented read from "
554  "address 0x%x ]\n", (int)relative_addr);
555  }
556  }
557 
558  if (writeflag == MEM_READ)
559  memory_writemax64(cpu, data, len, odata);
560 
561  return 1;
562 }
563 
564 
565 /*
566  * dev_jazz_jazzio_access():
567  *
568  * See jazzio_intr() in NetBSD's
569  * /usr/src/sys/arch/arc/jazz/jazzio.c for more info.
570  */
571 DEVICE_ACCESS(jazz_jazzio)
572 {
573  struct jazz_data *d = (struct jazz_data *) extra;
574  uint64_t idata = 0, odata = 0;
575  int i, v;
576 
577  if (writeflag == MEM_WRITE)
578  idata = memory_readmax64(cpu, data, len);
579 
580  switch (relative_addr) {
581  case 0:
582  v = 0;
583  for (i=0; i<15; i++) {
584  if (d->int_asserted & (1<<i)) {
585  v = i+1;
586  break;
587  }
588  }
589  odata = v << 2;
590  break;
591  case 2:
592  /* TODO: Should this be here?! */
593 
594  if (writeflag == MEM_WRITE)
595  d->jazz_timer_value = idata;
596  else
597  odata = d->jazz_timer_value;
598  break;
599  default:
600  if (writeflag == MEM_WRITE) {
601  fatal("[ jazzio: unimplemented write to address 0x%x"
602  ", data=0x%02x ]\n", (int)relative_addr,
603  (int)idata);
604  } else {
605  fatal("[ jazzio: unimplemented read from address 0x%x"
606  " ]\n", (int)relative_addr);
607  }
608  }
609 
610  /* This is needed by Windows NT during startup: */
612 
613  if (writeflag == MEM_READ)
614  memory_writemax64(cpu, data, len, odata);
615 
616  return 1;
617 }
618 
619 
620 DEVINIT(jazz)
621 {
622  struct jazz_data *d;
623  char tmpstr[300];
624  int i;
625 
626  CHECK_ALLOCATION(d = (struct jazz_data *) malloc(sizeof(struct jazz_data)));
627  memset(d, 0, sizeof(struct jazz_data));
628 
629  d->cpu = devinit->machine->cpus[0]; /* TODO */
630 
631  d->isa_int_enable_mask = 0xffff;
632 
633  /*
634  * Register 16 native JAZZ irqs, and 16 ISA irqs:
635  *
636  * machine[y].cpu[z].jazz.%i (native)
637  * machine[y].cpu[z].jazz.isa.%i (ISA)
638  */
639  for (i=0; i<16; i++) {
640  struct interrupt templ;
641  char n[300];
642  snprintf(n, sizeof(n), "%s.jazz.%i",
643  devinit->interrupt_path, i);
644  memset(&templ, 0, sizeof(templ));
645  templ.line = i;
646  templ.name = n;
647  templ.extra = d;
651  }
652  for (i=0; i<16; i++) {
653  struct interrupt templ;
654  char n[300];
655  snprintf(n, sizeof(n), "%s.jazz.isa.%i",
656  devinit->interrupt_path, i);
657  memset(&templ, 0, sizeof(templ));
658  templ.line = i;
659  templ.name = n;
660  templ.extra = d;
664  }
665 
666  /* Connect to MIPS CPU interrupt lines: */
667  snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
668  INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
669  snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
670  INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
671  snprintf(tmpstr, sizeof(tmpstr), "%s.6", devinit->interrupt_path);
672  INTERRUPT_CONNECT(tmpstr, d->mips_irq_6);
673 
674  /* Connect to JAZZ timer interrupt: */
675  snprintf(tmpstr, sizeof(tmpstr), "%s.jazz.%i",
677  INTERRUPT_CONNECT(tmpstr, d->jazz_timer_irq);
678 
681  dev_jazz_access, (void *)d, DM_DEFAULT, NULL);
682 
683  /* At least for Magnum and Pica-61: */
685  0x08000f000ULL, 4, dev_jazz_led_access, (void *)d,
686  DM_DEFAULT, NULL);
687 
688  memory_device_register(devinit->machine->memory, "jazz_isa_20",
689  0x90000020ULL, 2, dev_jazz_20_access, (void *)d, DM_DEFAULT, NULL);
690 
691  memory_device_register(devinit->machine->memory, "jazz_isa_a0",
692  0x900000a0ULL, 2, dev_jazz_a0_access, (void *)d, DM_DEFAULT, NULL);
693 
694  memory_device_register(devinit->machine->memory, "pica_jazzio",
695  0xf0000000ULL, 4, dev_jazz_jazzio_access, (void *)d,
696  DM_DEFAULT, NULL);
697 
698  /* Add a timer, hardcoded to 100 Hz. TODO: Don't hardcode! */
699  d->timer = timer_add(100.0, timer_tick, d);
700  machine_add_tickfunction(devinit->machine, dev_jazz_tick,
701  d, DEV_JAZZ_TICKSHIFT);
702 
703  devinit->return_ptr = d;
704 
705  return 1;
706 }
707 
R4030_DMA_ENAB_RUN
#define R4030_DMA_ENAB_RUN
Definition: jazz_r4030_dma.h:73
R4030_SYS_TL_BASE
#define R4030_SYS_TL_BASE
Definition: pica.h:73
pica.h
data
u_short data
Definition: siireg.h:79
timer_add
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
Definition: timer.cc:75
jazz_data::led
int led
Definition: dev_jazz.cc:100
R4030_SYS_DMA1_REGS
#define R4030_SYS_DMA1_REGS
Definition: pica.h:77
jazz_data::dma1_mode
uint32_t dma1_mode
Definition: dev_jazz.cc:97
jazz_data::int_enable_mask
uint32_t int_enable_mask
Definition: dev_jazz.cc:73
INTERRUPT_CONNECT
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
INTERRUPT_ASSERT
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
interrupt::interrupt_deassert
void(* interrupt_deassert)(struct interrupt *)
Definition: interrupt.h:39
timer
Definition: timer.cc:45
DEV_JAZZ_TICKSHIFT
#define DEV_JAZZ_TICKSHIFT
Definition: dev_jazz.cc:62
jazz_interrupt_deassert
void jazz_interrupt_deassert(struct interrupt *interrupt)
Definition: dev_jazz.cc:123
debug
#define debug
Definition: dev_adb.cc:57
jazz_data::interval
int interval
Definition: dev_jazz.cc:80
jazz_data::jazz_timer_irq
struct interrupt jazz_timer_irq
Definition: dev_jazz.cc:87
DEVICE_TICK
DEVICE_TICK(jazz)
Definition: dev_jazz.cc:234
machine::cpus
struct cpu ** cpus
Definition: machine.h:140
jazz_data::pending_timer_interrupts
int pending_timer_interrupts
Definition: dev_jazz.cc:84
jazz_data::dma_translation_table_base
uint64_t dma_translation_table_base
Definition: dev_jazz.cc:89
devinit::addr
uint64_t addr
Definition: device.h:46
jazz_data::timer
struct timer * timer
Definition: dev_jazz.cc:83
memory_device_register
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
jazz_data::isa_int_asserted
uint32_t isa_int_asserted
Definition: dev_jazz.cc:78
jazz_data::mips_irq_3
struct interrupt mips_irq_3
Definition: dev_jazz.cc:66
MEM_READ
#define MEM_READ
Definition: memory.h:116
DEVINIT
DEVINIT(jazz)
Definition: dev_jazz.cc:620
t
vmrs t
Definition: armreg.h:750
jazz_interrupt_assert
void jazz_interrupt_assert(struct interrupt *interrupt)
Definition: dev_jazz.cc:113
cpu::byte_order
uint8_t byte_order
Definition: cpu.h:347
EMUL_BIG_ENDIAN
#define EMUL_BIG_ENDIAN
Definition: misc.h:165
DM_DEFAULT
#define DM_DEFAULT
Definition: memory.h:130
interrupt::extra
void * extra
Definition: interrupt.h:59
devinit::machine
struct machine * machine
Definition: device.h:41
dev_jazz_dma_controller
size_t dev_jazz_dma_controller(void *dma_controller_data, unsigned char *data, size_t len, int writeflag)
Definition: dev_jazz.cc:150
jazz_data::isa_int_enable_mask
uint32_t isa_int_enable_mask
Definition: dev_jazz.cc:77
R4030_SYS_TL_LIMIT
#define R4030_SYS_TL_LIMIT
Definition: pica.h:74
device.h
MEM_WRITE
#define MEM_WRITE
Definition: memory.h:117
jazz_data::dma0_addr
uint32_t dma0_addr
Definition: dev_jazz.cc:95
jazz_r4030_dma.h
machine_add_tickfunction
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
jazz_data::mips_irq_6
struct interrupt mips_irq_6
Definition: dev_jazz.cc:68
devinit::interrupt_path
char * interrupt_path
Definition: device.h:50
R4030_SYS_TL_IVALID
#define R4030_SYS_TL_IVALID
Definition: pica.h:75
interrupt.h
PHYSICAL
#define PHYSICAL
Definition: memory.h:126
fatal
void fatal(const char *fmt,...)
Definition: main.cc:152
jazz_data::interval_start
int interval_start
Definition: dev_jazz.cc:81
R4030_SYS_DMA0_REGS
#define R4030_SYS_DMA0_REGS
Definition: pica.h:76
jazz_data::cpu
struct cpu * cpu
Definition: dev_jazz.cc:70
misc.h
DEVICE_ACCESS
DEVICE_ACCESS(jazz)
Definition: dev_jazz.cc:267
jazz_data::dma0_mode
uint32_t dma0_mode
Definition: dev_jazz.cc:92
memory_readmax64
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
machine.h
timer.h
jazz_data::jazz_timer_current
int jazz_timer_current
Definition: dev_jazz.cc:86
DEV_JAZZ_LENGTH
#define DEV_JAZZ_LENGTH
Definition: dev_jazz.cc:61
devinit
Definition: device.h:40
jazz_data::int_asserted
uint32_t int_asserted
Definition: dev_jazz.cc:74
cpu.h
PICA_TIMER_IRQ
#define PICA_TIMER_IRQ
Definition: dev_jazz.cc:63
machine::memory
struct memory * memory
Definition: machine.h:126
cpu::mem
struct memory * mem
Definition: cpu.h:362
R4030_SYS_EXT_IMASK
#define R4030_SYS_EXT_IMASK
Definition: pica.h:85
devinit::return_ptr
void * return_ptr
Definition: device.h:56
jazz_data::dma0_enable
uint32_t dma0_enable
Definition: dev_jazz.cc:93
NO_EXCEPTIONS
#define NO_EXCEPTIONS
Definition: memory.h:125
jazz_data::dma_translation_table_limit
uint64_t dma_translation_table_limit
Definition: dev_jazz.cc:90
R4030_SYS_ISA_VECTOR
#define R4030_SYS_ISA_VECTOR
Definition: pica.h:84
R4030_DMA_ENAB_WRITE
#define R4030_DMA_ENAB_WRITE
Definition: jazz_r4030_dma.h:75
INTERRUPT_DEASSERT
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75
interrupt::line
uint32_t line
Definition: interrupt.h:51
interrupt::interrupt_assert
void(* interrupt_assert)(struct interrupt *)
Definition: interrupt.h:38
jazz_isa_interrupt_deassert
void jazz_isa_interrupt_deassert(struct interrupt *interrupt)
Definition: dev_jazz.cc:139
interrupt_handler_register
void interrupt_handler_register(struct interrupt *templ)
Definition: interrupt.cc:81
interrupt::name
char * name
Definition: interrupt.h:66
jazz_data
Definition: dev_jazz.cc:65
interrupt
Definition: interrupt.h:36
memory_writemax64
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
R4030_SYS_IT_STAT
#define R4030_SYS_IT_STAT
Definition: pica.h:83
jazz_data::dma0_count
uint32_t dma0_count
Definition: dev_jazz.cc:94
R4030_SYS_IT_VALUE
#define R4030_SYS_IT_VALUE
Definition: pica.h:82
devices.h
cpu
Definition: cpu.h:326
reassert_isa_interrupts
void reassert_isa_interrupts(struct jazz_data *d)
Definition: dev_jazz.cc:104
jazz_isa_interrupt_assert
void jazz_isa_interrupt_assert(struct interrupt *interrupt)
Definition: dev_jazz.cc:133
cpu::memory_rw
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
Definition: cpu.h:365
jazz_data::jazz_timer_value
int jazz_timer_value
Definition: dev_jazz.cc:85
R4030_SYS_CONFIG
#define R4030_SYS_CONFIG
Definition: pica.h:72
memory.h
jazz_data::mips_irq_4
struct interrupt mips_irq_4
Definition: dev_jazz.cc:67
CHECK_ALLOCATION
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239

Generated on Tue Mar 24 2020 14:04:48 for GXemul by doxygen 1.8.17