Go to the source code of this file.
Macros | |
#define | HI6_NAMES |
#define | REGIMM_NAMES |
#define | SPECIAL_NAMES |
#define | SPECIAL_ROT_NAMES |
#define | SPECIAL2_NAMES |
#define | MMI_NAMES |
#define | MMI0_NAMES |
#define | MMI1_NAMES |
#define | MMI2_NAMES |
#define | MMI3_NAMES |
#define | SPECIAL3_NAMES |
#define | HI6_SPECIAL 0x00 /* 000000 */ |
#define | SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */ |
#define | SPECIAL_SRL 0x02 /* 000010 */ /* MIPS I */ |
#define | SPECIAL_SRA 0x03 /* 000011 */ /* MIPS I */ |
#define | SPECIAL_SLLV 0x04 /* 000100 */ /* MIPS I */ |
#define | SPECIAL_SRLV 0x06 /* 000110 */ |
#define | SPECIAL_SRAV 0x07 /* 000111 */ /* MIPS I */ |
#define | SPECIAL_JR 0x08 /* 001000 */ /* MIPS I */ |
#define | SPECIAL_JALR 0x09 /* 001001 */ /* MIPS I */ |
#define | SPECIAL_MOVZ 0x0a /* 001010 */ /* MIPS IV */ |
#define | SPECIAL_MOVN 0x0b /* 001011 */ /* MIPS IV */ |
#define | SPECIAL_SYSCALL 0x0c /* 001100 */ /* MIPS I */ |
#define | SPECIAL_BREAK 0x0d /* 001101 */ /* MIPS I */ |
#define | SPECIAL_SYNC 0x0f /* 001111 */ /* MIPS II */ |
#define | SPECIAL_MFHI 0x10 /* 010000 */ /* MIPS I */ |
#define | SPECIAL_MTHI 0x11 /* 010001 */ /* MIPS I */ |
#define | SPECIAL_MFLO 0x12 /* 010010 */ /* MIPS I */ |
#define | SPECIAL_MTLO 0x13 /* 010011 */ /* MIPS I */ |
#define | SPECIAL_DSLLV 0x14 /* 010100 */ |
#define | SPECIAL_DSRLV 0x16 /* 010110 */ /* MIPS III */ |
#define | SPECIAL_DSRAV 0x17 /* 010111 */ /* MIPS III */ |
#define | SPECIAL_MULT 0x18 /* 011000 */ /* MIPS I */ |
#define | SPECIAL_MULTU 0x19 /* 011001 */ /* MIPS I */ |
#define | SPECIAL_DIV 0x1a /* 011010 */ /* MIPS I */ |
#define | SPECIAL_DIVU 0x1b /* 011011 */ /* MIPS I */ |
#define | SPECIAL_DMULT 0x1c /* 011100 */ /* MIPS III */ |
#define | SPECIAL_DMULTU 0x1d /* 011101 */ /* MIPS III */ |
#define | SPECIAL_DDIV 0x1e /* 011110 */ /* MIPS III */ |
#define | SPECIAL_DDIVU 0x1f /* 011111 */ /* MIPS III */ |
#define | SPECIAL_ADD 0x20 /* 100000 */ /* MIPS I */ |
#define | SPECIAL_ADDU 0x21 /* 100001 */ /* MIPS I */ |
#define | SPECIAL_SUB 0x22 /* 100010 */ /* MIPS I */ |
#define | SPECIAL_SUBU 0x23 /* 100011 */ /* MIPS I */ |
#define | SPECIAL_AND 0x24 /* 100100 */ /* MIPS I */ |
#define | SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */ |
#define | SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */ |
#define | SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */ |
#define | SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */ |
#define | SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */ |
#define | SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */ |
#define | SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */ |
#define | SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */ |
#define | SPECIAL_DADDU 0x2d /* 101101 */ /* MIPS III */ |
#define | SPECIAL_DSUB 0x2e /* 101110 */ |
#define | SPECIAL_DSUBU 0x2f /* 101111 */ /* MIPS III */ |
#define | SPECIAL_TGE 0x30 /* 110000 */ |
#define | SPECIAL_TGEU 0x31 /* 110001 */ |
#define | SPECIAL_TLT 0x32 /* 110010 */ |
#define | SPECIAL_TLTU 0x33 /* 110011 */ |
#define | SPECIAL_TEQ 0x34 /* 110100 */ |
#define | SPECIAL_TNE 0x36 /* 110110 */ |
#define | SPECIAL_DSLL 0x38 /* 111000 */ /* MIPS III */ |
#define | SPECIAL_DSRL 0x3a /* 111010 */ /* MIPS III */ |
#define | SPECIAL_DSRA 0x3b /* 111011 */ /* MIPS III */ |
#define | SPECIAL_DSLL32 0x3c /* 111100 */ /* MIPS III */ |
#define | SPECIAL_DSRL32 0x3e /* 111110 */ /* MIPS III */ |
#define | SPECIAL_DSRA32 0x3f /* 111111 */ /* MIPS III */ |
#define | HI6_REGIMM 0x01 /* 000001 */ |
#define | REGIMM_BLTZ 0x00 /* 00000 */ /* MIPS I */ |
#define | REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */ |
#define | REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */ |
#define | REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */ |
#define | REGIMM_TGEI 0x08 /* 01000 */ |
#define | REGIMM_TGEIU 0x09 /* 01001 */ |
#define | REGIMM_TLTI 0x0a /* 01010 */ |
#define | REGIMM_TLTIU 0x0b /* 01011 */ |
#define | REGIMM_TEQI 0x0c /* 01100 */ |
#define | REGIMM_TNEI 0x0e /* 01110 */ |
#define | REGIMM_BLTZAL 0x10 /* 10000 */ |
#define | REGIMM_BGEZAL 0x11 /* 10001 */ |
#define | REGIMM_BLTZALL 0x12 /* 10010 */ |
#define | REGIMM_BGEZALL 0x13 /* 10011 */ |
#define | REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */ |
#define | REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */ |
#define | REGIMM_SYNCI 0x1f /* 11111 */ |
#define | HI6_J 0x02 /* 000010 */ /* MIPS I */ |
#define | HI6_JAL 0x03 /* 000011 */ /* MIPS I */ |
#define | HI6_BEQ 0x04 /* 000100 */ /* MIPS I */ |
#define | HI6_BNE 0x05 /* 000101 */ |
#define | HI6_BLEZ 0x06 /* 000110 */ /* MIPS I */ |
#define | HI6_BGTZ 0x07 /* 000111 */ /* MIPS I */ |
#define | HI6_ADDI 0x08 /* 001000 */ /* MIPS I */ |
#define | HI6_ADDIU 0x09 /* 001001 */ /* MIPS I */ |
#define | HI6_SLTI 0x0a /* 001010 */ /* MIPS I */ |
#define | HI6_SLTIU 0x0b /* 001011 */ /* MIPS I */ |
#define | HI6_ANDI 0x0c /* 001100 */ /* MIPS I */ |
#define | HI6_ORI 0x0d /* 001101 */ /* MIPS I */ |
#define | HI6_XORI 0x0e /* 001110 */ /* MIPS I */ |
#define | HI6_LUI 0x0f /* 001111 */ /* MIPS I */ |
#define | HI6_COP0 0x10 /* 010000 */ |
#define | COPz_MFCz 0x00 /* 00000 */ |
#define | COPz_DMFCz 0x01 /* 00001 */ |
#define | COPz_MTCz 0x04 /* 00100 */ |
#define | COPz_DMTCz 0x05 /* 00101 */ |
#define | COPz_CFCz 0x02 /* 00010 */ /* MIPS I */ |
#define | COPz_CTCz 0x06 /* 00110 */ /* MIPS I */ |
#define | COPz_BCzc 0x08 /* 01000 */ |
#define | COPz_MFMCz 0x0b /* 01011 */ |
#define | COP1_FMT_S 0x10 /* 10000 */ |
#define | COP1_FMT_D 0x11 /* 10001 */ |
#define | COP1_FMT_W 0x14 /* 10100 */ |
#define | COP1_FMT_L 0x15 /* 10101 */ |
#define | COP1_FMT_PS 0x16 /* 10110 */ |
#define | COP0_TLBR 0x01 /* 000001 */ |
#define | COP0_TLBWI 0x02 /* 000010 */ |
#define | COP0_TLBWR 0x06 /* 000110 */ |
#define | COP0_TLBP 0x08 /* 001000 */ |
#define | COP0_RFE 0x10 /* 010000 */ |
#define | COP0_ERET 0x18 /* 011000 */ |
#define | COP0_DERET 0x1f /* 011111 */ /* EJTAG */ |
#define | COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */ |
#define | COP0_STANDBY 0x21 /* 100001 */ |
#define | COP0_SUSPEND 0x22 /* 100010 */ |
#define | COP0_HIBERNATE 0x23 /* 100011 */ |
#define | COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */ |
#define | COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */ |
#define | HI6_COP1 0x11 /* 010001 */ |
#define | HI6_COP2 0x12 /* 010010 */ |
#define | HI6_COP3 0x13 /* 010011 */ |
#define | HI6_BEQL 0x14 /* 010100 */ /* MIPS II */ |
#define | HI6_BNEL 0x15 /* 010101 */ |
#define | HI6_BLEZL 0x16 /* 010110 */ /* MIPS II */ |
#define | HI6_BGTZL 0x17 /* 010111 */ /* MIPS II */ |
#define | HI6_DADDI 0x18 /* 011000 */ /* MIPS III */ |
#define | HI6_DADDIU 0x19 /* 011001 */ /* MIPS III */ |
#define | HI6_LDL 0x1a /* 011010 */ /* MIPS III */ |
#define | HI6_LDR 0x1b /* 011011 */ /* MIPS III */ |
#define | HI6_SPECIAL2 0x1c /* 011100 */ |
#define | SPECIAL2_MADD 0x00 /* 000000 */ /* MIPS32 (?) TODO */ |
#define | SPECIAL2_MADDU 0x01 /* 000001 */ /* MIPS32 (?) TODO */ |
#define | SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */ |
#define | SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */ |
#define | SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */ |
#define | SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */ |
#define | SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */ |
#define | SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */ |
#define | SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */ |
#define | SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */ |
#define | MMI_MADD 0x00 |
#define | MMI_MADDU 0x01 |
#define | MMI_PLZCW 0x04 |
#define | MMI_MMI0 0x08 |
#define | MMI0_PADDW 0x00 |
#define | MMI0_PSUBW 0x01 |
#define | MMI0_PCGTW 0x02 |
#define | MMI0_PMAXW 0x03 |
#define | MMI0_PADDH 0x04 |
#define | MMI0_PSUBH 0x05 |
#define | MMI0_PCGTH 0x06 |
#define | MMI0_PMAXH 0x07 |
#define | MMI0_PADDB 0x08 |
#define | MMI0_PSUBB 0x09 |
#define | MMI0_PCGTB 0x0a |
#define | MMI0_PADDSW 0x10 |
#define | MMI0_PSUBSW 0x11 |
#define | MMI0_PEXTLW 0x12 |
#define | MMI0_PPACW 0x13 |
#define | MMI0_PADDSH 0x14 |
#define | MMI0_PSUBSH 0x15 |
#define | MMI0_PEXTLH 0x16 |
#define | MMI0_PPACH 0x17 |
#define | MMI0_PADDSB 0x18 |
#define | MMI0_PSUBSB 0x19 |
#define | MMI0_PEXTLB 0x1a |
#define | MMI0_PPACB 0x1b |
#define | MMI0_PEXT5 0x1e |
#define | MMI0_PPAC5 0x1f |
#define | MMI_MMI2 0x09 |
#define | MMI2_PMADDW 0x00 |
#define | MMI2_PSLLVW 0x02 |
#define | MMI2_PSRLVW 0x03 |
#define | MMI2_PMSUBW 0x04 |
#define | MMI2_PMFHI 0x08 |
#define | MMI2_PMFLO 0x09 |
#define | MMI2_PINTH 0x0a |
#define | MMI2_PMULTW 0x0c |
#define | MMI2_PDIVW 0x0d |
#define | MMI2_PCPYLD 0x0e |
#define | MMI2_PMADDH 0x10 |
#define | MMI2_PHMADH 0x11 |
#define | MMI2_PAND 0x12 |
#define | MMI2_PXOR 0x13 |
#define | MMI2_PMSUBH 0x14 |
#define | MMI2_PHMSBH 0x15 |
#define | MMI2_PEXEH 0x1a |
#define | MMI2_PREVH 0x1b |
#define | MMI2_PMULTH 0x1c |
#define | MMI2_PDIVBW 0x1d |
#define | MMI2_PEXEW 0x1e |
#define | MMI2_PROT3W 0x1f |
#define | MMI_MFHI1 0x10 |
#define | MMI_MTHI1 0x11 |
#define | MMI_MFLO1 0x12 |
#define | MMI_MTLO1 0x13 |
#define | MMI_MULT1 0x18 |
#define | MMI_MULTU1 0x19 |
#define | MMI_DIV1 0x1a |
#define | MMI_DIVU1 0x1b |
#define | MMI_MADD1 0x20 |
#define | MMI_MADDU1 0x21 |
#define | MMI_MMI1 0x28 |
#define | MMI1_PABSW 0x01 |
#define | MMI1_PCEQW 0x02 |
#define | MMI1_PMINW 0x03 |
#define | MMI1_PADSBH 0x04 |
#define | MMI1_PABSH 0x05 |
#define | MMI1_PCEQH 0x06 |
#define | MMI1_PMINH 0x07 |
#define | MMI1_PCEQB 0x0a |
#define | MMI1_PADDUW 0x10 |
#define | MMI1_PSUBUW 0x11 |
#define | MMI1_PEXTUW 0x12 |
#define | MMI1_PADDUH 0x14 |
#define | MMI1_PSUBUH 0x15 |
#define | MMI1_PEXTUH 0x16 |
#define | MMI1_PADDUB 0x18 |
#define | MMI1_PSUBUB 0x19 |
#define | MMI1_PEXTUB 0x1a |
#define | MMI1_QFSRV 0x1b |
#define | MMI_MMI3 0x29 |
#define | MMI3_PMADDUW 0x00 |
#define | MMI3_PSRAVW 0x03 |
#define | MMI3_PMTHI 0x08 |
#define | MMI3_PMTLO 0x09 |
#define | MMI3_PINTEH 0x0a |
#define | MMI3_PMULTUW 0x0c |
#define | MMI3_PDIVUW 0x0d |
#define | MMI3_PCPYUD 0x0e |
#define | MMI3_POR 0x12 |
#define | MMI3_PNOR 0x13 |
#define | MMI3_PEXCH 0x1a |
#define | MMI3_PCPYH 0x1b |
#define | MMI3_PEXCW 0x1e |
#define | MMI_PMFHL 0x30 |
#define | MMI_PMTHL 0x31 |
#define | MMI_PSLLH 0x34 |
#define | MMI_PSRLH 0x36 |
#define | MMI_PSRAH 0x37 |
#define | MMI_PSLLW 0x3c |
#define | MMI_PSRLW 0x3e |
#define | MMI_PSRAW 0x3f |
#define | HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */ |
#define | HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */ |
#define | SPECIAL3_EXT 0x00 /* 000000 */ |
#define | SPECIAL3_DEXTM 0x01 /* 000001 */ |
#define | SPECIAL3_DEXTU 0x02 /* 000010 */ |
#define | SPECIAL3_DEXT 0x03 /* 000011 */ |
#define | SPECIAL3_INS 0x04 /* 000100 */ |
#define | SPECIAL3_DINSM 0x05 /* 000101 */ |
#define | SPECIAL3_DINSU 0x06 /* 000110 */ |
#define | SPECIAL3_DINS 0x07 /* 000111 */ |
#define | SPECIAL3_BSHFL 0x20 /* 100000 */ |
#define | BSHFL_WSBH 0x002 /* 00000..00010 */ |
#define | BSHFL_SEB 0x010 /* 00000..10000 */ |
#define | BSHFL_SEH 0x018 /* 00000..11000 */ |
#define | SPECIAL3_DBSHFL 0x24 /* 100100 */ |
#define | BSHFL_DSBH 0x002 /* 00000..00010 */ |
#define | BSHFL_DSHD 0x005 /* 00000..00101 */ |
#define | SPECIAL3_RDHWR 0x3b /* 111011 */ |
#define | HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
#define | HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
#define | HI6_LWL 0x22 /* 100010 */ /* MIPS I */ |
#define | HI6_LW 0x23 /* 100011 */ /* MIPS I */ |
#define | HI6_LBU 0x24 /* 100100 */ /* MIPS I */ |
#define | HI6_LHU 0x25 /* 100101 */ /* MIPS I */ |
#define | HI6_LWR 0x26 /* 100110 */ /* MIPS I */ |
#define | HI6_LWU 0x27 /* 100111 */ /* MIPS III */ |
#define | HI6_SB 0x28 /* 101000 */ /* MIPS I */ |
#define | HI6_SH 0x29 /* 101001 */ /* MIPS I */ |
#define | HI6_SWL 0x2a /* 101010 */ /* MIPS I */ |
#define | HI6_SW 0x2b /* 101011 */ /* MIPS I */ |
#define | HI6_SDL 0x2c /* 101100 */ /* MIPS III */ |
#define | HI6_SDR 0x2d /* 101101 */ /* MIPS III */ |
#define | HI6_SWR 0x2e /* 101110 */ /* MIPS I */ |
#define | HI6_CACHE 0x2f /* 101111 */ /* ??? R4000 */ |
#define | HI6_LL 0x30 /* 110000 */ /* MIPS II */ |
#define | HI6_LWC1 0x31 /* 110001 */ /* MIPS I */ |
#define | HI6_LWC2 0x32 /* 110010 */ /* MIPS I */ |
#define | HI6_LWC3 0x33 /* 110011 */ /* MIPS I */ |
#define | HI6_LLD 0x34 /* 110100 */ /* MIPS III */ |
#define | HI6_LDC1 0x35 /* 110101 */ /* MIPS II */ |
#define | HI6_LDC2 0x36 /* 110110 */ /* MIPS II */ |
#define | HI6_LD 0x37 /* 110111 */ /* MIPS III */ |
#define | HI6_SC 0x38 /* 111000 */ /* MIPS II */ |
#define | HI6_SWC1 0x39 /* 111001 */ /* MIPS I */ |
#define | HI6_SWC2 0x3a /* 111010 */ /* MIPS I */ |
#define | HI6_SWC3 0x3b /* 111011 */ /* MIPS I */ |
#define | HI6_SCD 0x3c /* 111100 */ /* MIPS III */ |
#define | HI6_SDC1 0x3d /* 111101 */ /* MIPS II */ |
#define | HI6_SDC2 0x3e /* 111110 */ /* MIPS II */ |
#define | HI6_SD 0x3f /* 111111 */ /* MIPS III */ |
#define BSHFL_DSBH 0x002 /* 00000..00010 */ |
Definition at line 445 of file opcodes_mips.h.
#define BSHFL_DSHD 0x005 /* 00000..00101 */ |
Definition at line 446 of file opcodes_mips.h.
#define BSHFL_SEB 0x010 /* 00000..10000 */ |
Definition at line 442 of file opcodes_mips.h.
#define BSHFL_SEH 0x018 /* 00000..11000 */ |
Definition at line 443 of file opcodes_mips.h.
#define BSHFL_WSBH 0x002 /* 00000..00010 */ |
Definition at line 441 of file opcodes_mips.h.
#define COP0_DERET 0x1f /* 011111 */ /* EJTAG */ |
Definition at line 295 of file opcodes_mips.h.
#define COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */ |
Definition at line 301 of file opcodes_mips.h.
#define COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */ |
Definition at line 300 of file opcodes_mips.h.
#define COP0_ERET 0x18 /* 011000 */ |
Definition at line 294 of file opcodes_mips.h.
#define COP0_HIBERNATE 0x23 /* 100011 */ |
Definition at line 299 of file opcodes_mips.h.
#define COP0_RFE 0x10 /* 010000 */ |
Definition at line 293 of file opcodes_mips.h.
#define COP0_STANDBY 0x21 /* 100001 */ |
Definition at line 297 of file opcodes_mips.h.
#define COP0_SUSPEND 0x22 /* 100010 */ |
Definition at line 298 of file opcodes_mips.h.
#define COP0_TLBP 0x08 /* 001000 */ |
Definition at line 292 of file opcodes_mips.h.
#define COP0_TLBR 0x01 /* 000001 */ |
Definition at line 289 of file opcodes_mips.h.
#define COP0_TLBWI 0x02 /* 000010 */ |
Definition at line 290 of file opcodes_mips.h.
#define COP0_TLBWR 0x06 /* 000110 */ |
Definition at line 291 of file opcodes_mips.h.
#define COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */ |
Definition at line 296 of file opcodes_mips.h.
#define COP1_FMT_D 0x11 /* 10001 */ |
Definition at line 284 of file opcodes_mips.h.
#define COP1_FMT_L 0x15 /* 10101 */ |
Definition at line 286 of file opcodes_mips.h.
#define COP1_FMT_PS 0x16 /* 10110 */ |
Definition at line 287 of file opcodes_mips.h.
#define COP1_FMT_S 0x10 /* 10000 */ |
Definition at line 283 of file opcodes_mips.h.
#define COP1_FMT_W 0x14 /* 10100 */ |
Definition at line 285 of file opcodes_mips.h.
#define COPz_BCzc 0x08 /* 01000 */ |
Definition at line 281 of file opcodes_mips.h.
#define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */ |
Definition at line 279 of file opcodes_mips.h.
#define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */ |
Definition at line 280 of file opcodes_mips.h.
#define COPz_DMFCz 0x01 /* 00001 */ |
Definition at line 270 of file opcodes_mips.h.
#define COPz_DMTCz 0x05 /* 00101 */ |
Definition at line 272 of file opcodes_mips.h.
#define COPz_MFCz 0x00 /* 00000 */ |
Definition at line 269 of file opcodes_mips.h.
#define COPz_MFMCz 0x0b /* 01011 */ |
Definition at line 282 of file opcodes_mips.h.
#define COPz_MTCz 0x04 /* 00100 */ |
Definition at line 271 of file opcodes_mips.h.
#define HI6_ADDI 0x08 /* 001000 */ /* MIPS I */ |
Definition at line 260 of file opcodes_mips.h.
#define HI6_ADDIU 0x09 /* 001001 */ /* MIPS I */ |
Definition at line 261 of file opcodes_mips.h.
#define HI6_ANDI 0x0c /* 001100 */ /* MIPS I */ |
Definition at line 264 of file opcodes_mips.h.
#define HI6_BEQ 0x04 /* 000100 */ /* MIPS I */ |
Definition at line 256 of file opcodes_mips.h.
#define HI6_BEQL 0x14 /* 010100 */ /* MIPS II */ |
Definition at line 305 of file opcodes_mips.h.
#define HI6_BGTZ 0x07 /* 000111 */ /* MIPS I */ |
Definition at line 259 of file opcodes_mips.h.
#define HI6_BGTZL 0x17 /* 010111 */ /* MIPS II */ |
Definition at line 308 of file opcodes_mips.h.
#define HI6_BLEZ 0x06 /* 000110 */ /* MIPS I */ |
Definition at line 258 of file opcodes_mips.h.
#define HI6_BLEZL 0x16 /* 010110 */ /* MIPS II */ |
Definition at line 307 of file opcodes_mips.h.
#define HI6_BNE 0x05 /* 000101 */ |
Definition at line 257 of file opcodes_mips.h.
#define HI6_BNEL 0x15 /* 010101 */ |
Definition at line 306 of file opcodes_mips.h.
#define HI6_CACHE 0x2f /* 101111 */ /* ??? R4000 */ |
Definition at line 463 of file opcodes_mips.h.
#define HI6_COP0 0x10 /* 010000 */ |
Definition at line 268 of file opcodes_mips.h.
#define HI6_COP1 0x11 /* 010001 */ |
Definition at line 302 of file opcodes_mips.h.
#define HI6_COP2 0x12 /* 010010 */ |
Definition at line 303 of file opcodes_mips.h.
#define HI6_COP3 0x13 /* 010011 */ |
Definition at line 304 of file opcodes_mips.h.
#define HI6_DADDI 0x18 /* 011000 */ /* MIPS III */ |
Definition at line 309 of file opcodes_mips.h.
#define HI6_DADDIU 0x19 /* 011001 */ /* MIPS III */ |
Definition at line 310 of file opcodes_mips.h.
#define HI6_J 0x02 /* 000010 */ /* MIPS I */ |
Definition at line 254 of file opcodes_mips.h.
#define HI6_JAL 0x03 /* 000011 */ /* MIPS I */ |
Definition at line 255 of file opcodes_mips.h.
#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
Definition at line 448 of file opcodes_mips.h.
#define HI6_LBU 0x24 /* 100100 */ /* MIPS I */ |
Definition at line 452 of file opcodes_mips.h.
#define HI6_LD 0x37 /* 110111 */ /* MIPS III */ |
Definition at line 471 of file opcodes_mips.h.
#define HI6_LDC1 0x35 /* 110101 */ /* MIPS II */ |
Definition at line 469 of file opcodes_mips.h.
#define HI6_LDC2 0x36 /* 110110 */ /* MIPS II */ |
Definition at line 470 of file opcodes_mips.h.
#define HI6_LDL 0x1a /* 011010 */ /* MIPS III */ |
Definition at line 311 of file opcodes_mips.h.
#define HI6_LDR 0x1b /* 011011 */ /* MIPS III */ |
Definition at line 312 of file opcodes_mips.h.
#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
Definition at line 449 of file opcodes_mips.h.
#define HI6_LHU 0x25 /* 100101 */ /* MIPS I */ |
Definition at line 453 of file opcodes_mips.h.
#define HI6_LL 0x30 /* 110000 */ /* MIPS II */ |
Definition at line 464 of file opcodes_mips.h.
#define HI6_LLD 0x34 /* 110100 */ /* MIPS III */ |
Definition at line 468 of file opcodes_mips.h.
#define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */ |
Definition at line 429 of file opcodes_mips.h.
#define HI6_LUI 0x0f /* 001111 */ /* MIPS I */ |
Definition at line 267 of file opcodes_mips.h.
#define HI6_LW 0x23 /* 100011 */ /* MIPS I */ |
Definition at line 451 of file opcodes_mips.h.
#define HI6_LWC1 0x31 /* 110001 */ /* MIPS I */ |
Definition at line 465 of file opcodes_mips.h.
#define HI6_LWC2 0x32 /* 110010 */ /* MIPS I */ |
Definition at line 466 of file opcodes_mips.h.
#define HI6_LWC3 0x33 /* 110011 */ /* MIPS I */ |
Definition at line 467 of file opcodes_mips.h.
#define HI6_LWL 0x22 /* 100010 */ /* MIPS I */ |
Definition at line 450 of file opcodes_mips.h.
#define HI6_LWR 0x26 /* 100110 */ /* MIPS I */ |
Definition at line 454 of file opcodes_mips.h.
#define HI6_LWU 0x27 /* 100111 */ /* MIPS III */ |
Definition at line 455 of file opcodes_mips.h.
#define HI6_NAMES |
Definition at line 60 of file opcodes_mips.h.
#define HI6_ORI 0x0d /* 001101 */ /* MIPS I */ |
Definition at line 265 of file opcodes_mips.h.
#define HI6_REGIMM 0x01 /* 000001 */ |
Definition at line 234 of file opcodes_mips.h.
#define HI6_SB 0x28 /* 101000 */ /* MIPS I */ |
Definition at line 456 of file opcodes_mips.h.
#define HI6_SC 0x38 /* 111000 */ /* MIPS II */ |
Definition at line 472 of file opcodes_mips.h.
#define HI6_SCD 0x3c /* 111100 */ /* MIPS III */ |
Definition at line 476 of file opcodes_mips.h.
#define HI6_SD 0x3f /* 111111 */ /* MIPS III */ |
Definition at line 479 of file opcodes_mips.h.
#define HI6_SDC1 0x3d /* 111101 */ /* MIPS II */ |
Definition at line 477 of file opcodes_mips.h.
#define HI6_SDC2 0x3e /* 111110 */ /* MIPS II */ |
Definition at line 478 of file opcodes_mips.h.
#define HI6_SDL 0x2c /* 101100 */ /* MIPS III */ |
Definition at line 460 of file opcodes_mips.h.
#define HI6_SDR 0x2d /* 101101 */ /* MIPS III */ |
Definition at line 461 of file opcodes_mips.h.
#define HI6_SH 0x29 /* 101001 */ /* MIPS I */ |
Definition at line 457 of file opcodes_mips.h.
#define HI6_SLTI 0x0a /* 001010 */ /* MIPS I */ |
Definition at line 262 of file opcodes_mips.h.
#define HI6_SLTIU 0x0b /* 001011 */ /* MIPS I */ |
Definition at line 263 of file opcodes_mips.h.
#define HI6_SPECIAL 0x00 /* 000000 */ |
Definition at line 168 of file opcodes_mips.h.
#define HI6_SPECIAL2 0x1c /* 011100 */ |
Definition at line 313 of file opcodes_mips.h.
#define HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */ |
Definition at line 431 of file opcodes_mips.h.
#define HI6_SW 0x2b /* 101011 */ /* MIPS I */ |
Definition at line 459 of file opcodes_mips.h.
#define HI6_SWC1 0x39 /* 111001 */ /* MIPS I */ |
Definition at line 473 of file opcodes_mips.h.
#define HI6_SWC2 0x3a /* 111010 */ /* MIPS I */ |
Definition at line 474 of file opcodes_mips.h.
#define HI6_SWC3 0x3b /* 111011 */ /* MIPS I */ |
Definition at line 475 of file opcodes_mips.h.
#define HI6_SWL 0x2a /* 101010 */ /* MIPS I */ |
Definition at line 458 of file opcodes_mips.h.
#define HI6_SWR 0x2e /* 101110 */ /* MIPS I */ |
Definition at line 462 of file opcodes_mips.h.
#define HI6_XORI 0x0e /* 001110 */ /* MIPS I */ |
Definition at line 266 of file opcodes_mips.h.
#define MMI0_NAMES |
Definition at line 118 of file opcodes_mips.h.
#define MMI0_PADDB 0x08 |
Definition at line 337 of file opcodes_mips.h.
#define MMI0_PADDH 0x04 |
Definition at line 333 of file opcodes_mips.h.
#define MMI0_PADDSB 0x18 |
Definition at line 348 of file opcodes_mips.h.
#define MMI0_PADDSH 0x14 |
Definition at line 344 of file opcodes_mips.h.
#define MMI0_PADDSW 0x10 |
Definition at line 340 of file opcodes_mips.h.
#define MMI0_PADDW 0x00 |
Definition at line 329 of file opcodes_mips.h.
#define MMI0_PCGTB 0x0a |
Definition at line 339 of file opcodes_mips.h.
#define MMI0_PCGTH 0x06 |
Definition at line 335 of file opcodes_mips.h.
#define MMI0_PCGTW 0x02 |
Definition at line 331 of file opcodes_mips.h.
#define MMI0_PEXT5 0x1e |
Definition at line 352 of file opcodes_mips.h.
#define MMI0_PEXTLB 0x1a |
Definition at line 350 of file opcodes_mips.h.
#define MMI0_PEXTLH 0x16 |
Definition at line 346 of file opcodes_mips.h.
#define MMI0_PEXTLW 0x12 |
Definition at line 342 of file opcodes_mips.h.
#define MMI0_PMAXH 0x07 |
Definition at line 336 of file opcodes_mips.h.
#define MMI0_PMAXW 0x03 |
Definition at line 332 of file opcodes_mips.h.
#define MMI0_PPAC5 0x1f |
Definition at line 353 of file opcodes_mips.h.
#define MMI0_PPACB 0x1b |
Definition at line 351 of file opcodes_mips.h.
#define MMI0_PPACH 0x17 |
Definition at line 347 of file opcodes_mips.h.
#define MMI0_PPACW 0x13 |
Definition at line 343 of file opcodes_mips.h.
#define MMI0_PSUBB 0x09 |
Definition at line 338 of file opcodes_mips.h.
#define MMI0_PSUBH 0x05 |
Definition at line 334 of file opcodes_mips.h.
#define MMI0_PSUBSB 0x19 |
Definition at line 349 of file opcodes_mips.h.
#define MMI0_PSUBSH 0x15 |
Definition at line 345 of file opcodes_mips.h.
#define MMI0_PSUBSW 0x11 |
Definition at line 341 of file opcodes_mips.h.
#define MMI0_PSUBW 0x01 |
Definition at line 330 of file opcodes_mips.h.
#define MMI1_NAMES |
Definition at line 128 of file opcodes_mips.h.
#define MMI1_PABSH 0x05 |
Definition at line 392 of file opcodes_mips.h.
#define MMI1_PABSW 0x01 |
Definition at line 388 of file opcodes_mips.h.
#define MMI1_PADDUB 0x18 |
Definition at line 402 of file opcodes_mips.h.
#define MMI1_PADDUH 0x14 |
Definition at line 399 of file opcodes_mips.h.
#define MMI1_PADDUW 0x10 |
Definition at line 396 of file opcodes_mips.h.
#define MMI1_PADSBH 0x04 |
Definition at line 391 of file opcodes_mips.h.
#define MMI1_PCEQB 0x0a |
Definition at line 395 of file opcodes_mips.h.
#define MMI1_PCEQH 0x06 |
Definition at line 393 of file opcodes_mips.h.
#define MMI1_PCEQW 0x02 |
Definition at line 389 of file opcodes_mips.h.
#define MMI1_PEXTUB 0x1a |
Definition at line 404 of file opcodes_mips.h.
#define MMI1_PEXTUH 0x16 |
Definition at line 401 of file opcodes_mips.h.
#define MMI1_PEXTUW 0x12 |
Definition at line 398 of file opcodes_mips.h.
#define MMI1_PMINH 0x07 |
Definition at line 394 of file opcodes_mips.h.
#define MMI1_PMINW 0x03 |
Definition at line 390 of file opcodes_mips.h.
#define MMI1_PSUBUB 0x19 |
Definition at line 403 of file opcodes_mips.h.
#define MMI1_PSUBUH 0x15 |
Definition at line 400 of file opcodes_mips.h.
#define MMI1_PSUBUW 0x11 |
Definition at line 397 of file opcodes_mips.h.
#define MMI1_QFSRV 0x1b |
Definition at line 405 of file opcodes_mips.h.
#define MMI2_NAMES |
Definition at line 138 of file opcodes_mips.h.
#define MMI2_PAND 0x12 |
Definition at line 367 of file opcodes_mips.h.
#define MMI2_PCPYLD 0x0e |
Definition at line 364 of file opcodes_mips.h.
#define MMI2_PDIVBW 0x1d |
Definition at line 374 of file opcodes_mips.h.
#define MMI2_PDIVW 0x0d |
Definition at line 363 of file opcodes_mips.h.
#define MMI2_PEXEH 0x1a |
Definition at line 371 of file opcodes_mips.h.
#define MMI2_PEXEW 0x1e |
Definition at line 375 of file opcodes_mips.h.
#define MMI2_PHMADH 0x11 |
Definition at line 366 of file opcodes_mips.h.
#define MMI2_PHMSBH 0x15 |
Definition at line 370 of file opcodes_mips.h.
#define MMI2_PINTH 0x0a |
Definition at line 361 of file opcodes_mips.h.
#define MMI2_PMADDH 0x10 |
Definition at line 365 of file opcodes_mips.h.
#define MMI2_PMADDW 0x00 |
Definition at line 355 of file opcodes_mips.h.
#define MMI2_PMFHI 0x08 |
Definition at line 359 of file opcodes_mips.h.
#define MMI2_PMFLO 0x09 |
Definition at line 360 of file opcodes_mips.h.
#define MMI2_PMSUBH 0x14 |
Definition at line 369 of file opcodes_mips.h.
#define MMI2_PMSUBW 0x04 |
Definition at line 358 of file opcodes_mips.h.
#define MMI2_PMULTH 0x1c |
Definition at line 373 of file opcodes_mips.h.
#define MMI2_PMULTW 0x0c |
Definition at line 362 of file opcodes_mips.h.
#define MMI2_PREVH 0x1b |
Definition at line 372 of file opcodes_mips.h.
#define MMI2_PROT3W 0x1f |
Definition at line 376 of file opcodes_mips.h.
#define MMI2_PSLLVW 0x02 |
Definition at line 356 of file opcodes_mips.h.
#define MMI2_PSRLVW 0x03 |
Definition at line 357 of file opcodes_mips.h.
#define MMI2_PXOR 0x13 |
Definition at line 368 of file opcodes_mips.h.
#define MMI3_NAMES |
Definition at line 148 of file opcodes_mips.h.
#define MMI3_PCPYH 0x1b |
Definition at line 418 of file opcodes_mips.h.
#define MMI3_PCPYUD 0x0e |
Definition at line 414 of file opcodes_mips.h.
#define MMI3_PDIVUW 0x0d |
Definition at line 413 of file opcodes_mips.h.
#define MMI3_PEXCH 0x1a |
Definition at line 417 of file opcodes_mips.h.
#define MMI3_PEXCW 0x1e |
Definition at line 419 of file opcodes_mips.h.
#define MMI3_PINTEH 0x0a |
Definition at line 411 of file opcodes_mips.h.
#define MMI3_PMADDUW 0x00 |
Definition at line 407 of file opcodes_mips.h.
#define MMI3_PMTHI 0x08 |
Definition at line 409 of file opcodes_mips.h.
#define MMI3_PMTLO 0x09 |
Definition at line 410 of file opcodes_mips.h.
#define MMI3_PMULTUW 0x0c |
Definition at line 412 of file opcodes_mips.h.
#define MMI3_PNOR 0x13 |
Definition at line 416 of file opcodes_mips.h.
#define MMI3_POR 0x12 |
Definition at line 415 of file opcodes_mips.h.
#define MMI3_PSRAVW 0x03 |
Definition at line 408 of file opcodes_mips.h.
#define MMI_DIV1 0x1a |
Definition at line 383 of file opcodes_mips.h.
#define MMI_DIVU1 0x1b |
Definition at line 384 of file opcodes_mips.h.
#define MMI_MADD 0x00 |
Definition at line 325 of file opcodes_mips.h.
#define MMI_MADD1 0x20 |
Definition at line 385 of file opcodes_mips.h.
#define MMI_MADDU 0x01 |
Definition at line 326 of file opcodes_mips.h.
#define MMI_MADDU1 0x21 |
Definition at line 386 of file opcodes_mips.h.
#define MMI_MFHI1 0x10 |
Definition at line 377 of file opcodes_mips.h.
#define MMI_MFLO1 0x12 |
Definition at line 379 of file opcodes_mips.h.
#define MMI_MMI0 0x08 |
Definition at line 328 of file opcodes_mips.h.
#define MMI_MMI1 0x28 |
Definition at line 387 of file opcodes_mips.h.
#define MMI_MMI2 0x09 |
Definition at line 354 of file opcodes_mips.h.
#define MMI_MMI3 0x29 |
Definition at line 406 of file opcodes_mips.h.
#define MMI_MTHI1 0x11 |
Definition at line 378 of file opcodes_mips.h.
#define MMI_MTLO1 0x13 |
Definition at line 380 of file opcodes_mips.h.
#define MMI_MULT1 0x18 |
Definition at line 381 of file opcodes_mips.h.
#define MMI_MULTU1 0x19 |
Definition at line 382 of file opcodes_mips.h.
#define MMI_NAMES |
Definition at line 108 of file opcodes_mips.h.
#define MMI_PLZCW 0x04 |
Definition at line 327 of file opcodes_mips.h.
#define MMI_PMFHL 0x30 |
Definition at line 420 of file opcodes_mips.h.
#define MMI_PMTHL 0x31 |
Definition at line 421 of file opcodes_mips.h.
#define MMI_PSLLH 0x34 |
Definition at line 422 of file opcodes_mips.h.
#define MMI_PSLLW 0x3c |
Definition at line 425 of file opcodes_mips.h.
#define MMI_PSRAH 0x37 |
Definition at line 424 of file opcodes_mips.h.
#define MMI_PSRAW 0x3f |
Definition at line 427 of file opcodes_mips.h.
#define MMI_PSRLH 0x36 |
Definition at line 423 of file opcodes_mips.h.
#define MMI_PSRLW 0x3e |
Definition at line 426 of file opcodes_mips.h.
#define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */ |
Definition at line 236 of file opcodes_mips.h.
#define REGIMM_BGEZAL 0x11 /* 10001 */ |
Definition at line 246 of file opcodes_mips.h.
#define REGIMM_BGEZALL 0x13 /* 10011 */ |
Definition at line 248 of file opcodes_mips.h.
#define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */ |
Definition at line 238 of file opcodes_mips.h.
#define REGIMM_BLTZ 0x00 /* 00000 */ /* MIPS I */ |
Definition at line 235 of file opcodes_mips.h.
#define REGIMM_BLTZAL 0x10 /* 10000 */ |
Definition at line 245 of file opcodes_mips.h.
#define REGIMM_BLTZALL 0x12 /* 10010 */ |
Definition at line 247 of file opcodes_mips.h.
#define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */ |
Definition at line 237 of file opcodes_mips.h.
#define REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */ |
Definition at line 249 of file opcodes_mips.h.
#define REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */ |
Definition at line 250 of file opcodes_mips.h.
#define REGIMM_NAMES |
Definition at line 70 of file opcodes_mips.h.
#define REGIMM_SYNCI 0x1f /* 11111 */ |
Definition at line 251 of file opcodes_mips.h.
#define REGIMM_TEQI 0x0c /* 01100 */ |
Definition at line 243 of file opcodes_mips.h.
#define REGIMM_TGEI 0x08 /* 01000 */ |
Definition at line 239 of file opcodes_mips.h.
#define REGIMM_TGEIU 0x09 /* 01001 */ |
Definition at line 240 of file opcodes_mips.h.
#define REGIMM_TLTI 0x0a /* 01010 */ |
Definition at line 241 of file opcodes_mips.h.
#define REGIMM_TLTIU 0x0b /* 01011 */ |
Definition at line 242 of file opcodes_mips.h.
#define REGIMM_TNEI 0x0e /* 01110 */ |
Definition at line 244 of file opcodes_mips.h.
#define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */ |
Definition at line 320 of file opcodes_mips.h.
#define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */ |
Definition at line 319 of file opcodes_mips.h.
#define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */ |
Definition at line 322 of file opcodes_mips.h.
#define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */ |
Definition at line 321 of file opcodes_mips.h.
#define SPECIAL2_MADD 0x00 /* 000000 */ /* MIPS32 (?) TODO */ |
Definition at line 314 of file opcodes_mips.h.
#define SPECIAL2_MADDU 0x01 /* 000001 */ /* MIPS32 (?) TODO */ |
Definition at line 315 of file opcodes_mips.h.
#define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */ |
Definition at line 317 of file opcodes_mips.h.
#define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */ |
Definition at line 318 of file opcodes_mips.h.
#define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */ |
Definition at line 316 of file opcodes_mips.h.
#define SPECIAL2_NAMES |
Definition at line 97 of file opcodes_mips.h.
#define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */ |
Definition at line 323 of file opcodes_mips.h.
#define SPECIAL3_BSHFL 0x20 /* 100000 */ |
Definition at line 440 of file opcodes_mips.h.
#define SPECIAL3_DBSHFL 0x24 /* 100100 */ |
Definition at line 444 of file opcodes_mips.h.
#define SPECIAL3_DEXT 0x03 /* 000011 */ |
Definition at line 435 of file opcodes_mips.h.
#define SPECIAL3_DEXTM 0x01 /* 000001 */ |
Definition at line 433 of file opcodes_mips.h.
#define SPECIAL3_DEXTU 0x02 /* 000010 */ |
Definition at line 434 of file opcodes_mips.h.
#define SPECIAL3_DINS 0x07 /* 000111 */ |
Definition at line 439 of file opcodes_mips.h.
#define SPECIAL3_DINSM 0x05 /* 000101 */ |
Definition at line 437 of file opcodes_mips.h.
#define SPECIAL3_DINSU 0x06 /* 000110 */ |
Definition at line 438 of file opcodes_mips.h.
#define SPECIAL3_EXT 0x00 /* 000000 */ |
Definition at line 432 of file opcodes_mips.h.
#define SPECIAL3_INS 0x04 /* 000100 */ |
Definition at line 436 of file opcodes_mips.h.
#define SPECIAL3_NAMES |
Definition at line 158 of file opcodes_mips.h.
#define SPECIAL3_RDHWR 0x3b /* 111011 */ |
Definition at line 447 of file opcodes_mips.h.
#define SPECIAL_ADD 0x20 /* 100000 */ /* MIPS I */ |
Definition at line 201 of file opcodes_mips.h.
#define SPECIAL_ADDU 0x21 /* 100001 */ /* MIPS I */ |
Definition at line 202 of file opcodes_mips.h.
#define SPECIAL_AND 0x24 /* 100100 */ /* MIPS I */ |
Definition at line 205 of file opcodes_mips.h.
#define SPECIAL_BREAK 0x0d /* 001101 */ /* MIPS I */ |
Definition at line 182 of file opcodes_mips.h.
#define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */ |
Definition at line 213 of file opcodes_mips.h.
#define SPECIAL_DADDU 0x2d /* 101101 */ /* MIPS III */ |
Definition at line 214 of file opcodes_mips.h.
#define SPECIAL_DDIV 0x1e /* 011110 */ /* MIPS III */ |
Definition at line 199 of file opcodes_mips.h.
#define SPECIAL_DDIVU 0x1f /* 011111 */ /* MIPS III */ |
Definition at line 200 of file opcodes_mips.h.
#define SPECIAL_DIV 0x1a /* 011010 */ /* MIPS I */ |
Definition at line 195 of file opcodes_mips.h.
#define SPECIAL_DIVU 0x1b /* 011011 */ /* MIPS I */ |
Definition at line 196 of file opcodes_mips.h.
#define SPECIAL_DMULT 0x1c /* 011100 */ /* MIPS III */ |
Definition at line 197 of file opcodes_mips.h.
#define SPECIAL_DMULTU 0x1d /* 011101 */ /* MIPS III */ |
Definition at line 198 of file opcodes_mips.h.
#define SPECIAL_DSLL 0x38 /* 111000 */ /* MIPS III */ |
Definition at line 225 of file opcodes_mips.h.
#define SPECIAL_DSLL32 0x3c /* 111100 */ /* MIPS III */ |
Definition at line 229 of file opcodes_mips.h.
#define SPECIAL_DSLLV 0x14 /* 010100 */ |
Definition at line 189 of file opcodes_mips.h.
#define SPECIAL_DSRA 0x3b /* 111011 */ /* MIPS III */ |
Definition at line 228 of file opcodes_mips.h.
#define SPECIAL_DSRA32 0x3f /* 111111 */ /* MIPS III */ |
Definition at line 232 of file opcodes_mips.h.
#define SPECIAL_DSRAV 0x17 /* 010111 */ /* MIPS III */ |
Definition at line 192 of file opcodes_mips.h.
#define SPECIAL_DSRL 0x3a /* 111010 */ /* MIPS III */ |
Definition at line 227 of file opcodes_mips.h.
#define SPECIAL_DSRL32 0x3e /* 111110 */ /* MIPS III */ |
Definition at line 231 of file opcodes_mips.h.
#define SPECIAL_DSRLV 0x16 /* 010110 */ /* MIPS III */ |
Definition at line 191 of file opcodes_mips.h.
#define SPECIAL_DSUB 0x2e /* 101110 */ |
Definition at line 215 of file opcodes_mips.h.
#define SPECIAL_DSUBU 0x2f /* 101111 */ /* MIPS III */ |
Definition at line 216 of file opcodes_mips.h.
#define SPECIAL_JALR 0x09 /* 001001 */ /* MIPS I */ |
Definition at line 178 of file opcodes_mips.h.
#define SPECIAL_JR 0x08 /* 001000 */ /* MIPS I */ |
Definition at line 177 of file opcodes_mips.h.
#define SPECIAL_MFHI 0x10 /* 010000 */ /* MIPS I */ |
Definition at line 185 of file opcodes_mips.h.
#define SPECIAL_MFLO 0x12 /* 010010 */ /* MIPS I */ |
Definition at line 187 of file opcodes_mips.h.
#define SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */ |
Definition at line 209 of file opcodes_mips.h.
#define SPECIAL_MOVN 0x0b /* 001011 */ /* MIPS IV */ |
Definition at line 180 of file opcodes_mips.h.
#define SPECIAL_MOVZ 0x0a /* 001010 */ /* MIPS IV */ |
Definition at line 179 of file opcodes_mips.h.
#define SPECIAL_MTHI 0x11 /* 010001 */ /* MIPS I */ |
Definition at line 186 of file opcodes_mips.h.
#define SPECIAL_MTLO 0x13 /* 010011 */ /* MIPS I */ |
Definition at line 188 of file opcodes_mips.h.
#define SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */ |
Definition at line 210 of file opcodes_mips.h.
#define SPECIAL_MULT 0x18 /* 011000 */ /* MIPS I */ |
Definition at line 193 of file opcodes_mips.h.
#define SPECIAL_MULTU 0x19 /* 011001 */ /* MIPS I */ |
Definition at line 194 of file opcodes_mips.h.
#define SPECIAL_NAMES |
Definition at line 76 of file opcodes_mips.h.
#define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */ |
Definition at line 208 of file opcodes_mips.h.
#define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */ |
Definition at line 206 of file opcodes_mips.h.
#define SPECIAL_ROT_NAMES |
Definition at line 87 of file opcodes_mips.h.
#define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */ |
Definition at line 169 of file opcodes_mips.h.
#define SPECIAL_SLLV 0x04 /* 000100 */ /* MIPS I */ |
Definition at line 173 of file opcodes_mips.h.
#define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */ |
Definition at line 211 of file opcodes_mips.h.
#define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */ |
Definition at line 212 of file opcodes_mips.h.
#define SPECIAL_SRA 0x03 /* 000011 */ /* MIPS I */ |
Definition at line 172 of file opcodes_mips.h.
#define SPECIAL_SRAV 0x07 /* 000111 */ /* MIPS I */ |
Definition at line 176 of file opcodes_mips.h.
#define SPECIAL_SRL 0x02 /* 000010 */ /* MIPS I */ |
Definition at line 171 of file opcodes_mips.h.
#define SPECIAL_SRLV 0x06 /* 000110 */ |
Definition at line 175 of file opcodes_mips.h.
#define SPECIAL_SUB 0x22 /* 100010 */ /* MIPS I */ |
Definition at line 203 of file opcodes_mips.h.
#define SPECIAL_SUBU 0x23 /* 100011 */ /* MIPS I */ |
Definition at line 204 of file opcodes_mips.h.
#define SPECIAL_SYNC 0x0f /* 001111 */ /* MIPS II */ |
Definition at line 184 of file opcodes_mips.h.
#define SPECIAL_SYSCALL 0x0c /* 001100 */ /* MIPS I */ |
Definition at line 181 of file opcodes_mips.h.
#define SPECIAL_TEQ 0x34 /* 110100 */ |
Definition at line 221 of file opcodes_mips.h.
#define SPECIAL_TGE 0x30 /* 110000 */ |
Definition at line 217 of file opcodes_mips.h.
#define SPECIAL_TGEU 0x31 /* 110001 */ |
Definition at line 218 of file opcodes_mips.h.
#define SPECIAL_TLT 0x32 /* 110010 */ |
Definition at line 219 of file opcodes_mips.h.
#define SPECIAL_TLTU 0x33 /* 110011 */ |
Definition at line 220 of file opcodes_mips.h.
#define SPECIAL_TNE 0x36 /* 110110 */ |
Definition at line 223 of file opcodes_mips.h.
#define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */ |
Definition at line 207 of file opcodes_mips.h.