Go to the source code of this file.
Macros | |
#define | XINE_PHYS_MIN 0x00000000 /* 512 Meg */ |
#define | XINE_PHYS_MAX 0x1fffffff |
#define | XINE_PHYS_MEMORY_START 0x00000000 |
#define | XINE_PHYS_MEMORY_END |
#define | XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */ |
#define | XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */ |
#define | XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ |
#define | XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ |
#define | XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ |
#define | XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ |
#define | XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ |
#define | XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ |
#define | XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ |
#define | XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ |
#define | XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */ |
#define | XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ |
#define | XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ |
#define | XINE_PHYS_TC_START XINE_PHYS_TC_0_START |
#define | XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */ |
#define | XINE_TC_NSLOTS 4 |
#define | XINE_TC_MIN 0 |
#define | XINE_TC_MAX 1 /* only option slots */ |
#define | XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) |
#define | XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START) |
#define | XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START) |
#define | XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START) |
#define | XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START) |
#define | XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START) |
#define | XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START) |
#define | XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START) |
#define | XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START) |
#define | XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START) |
#define | XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START) |
#define | XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START) |
#define | XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START) |
#define | XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START) |
#define | XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START) |
#define | XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) |
#define | XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) |
#define | XINE_INT_FPA IP_LEV7 /* Floating Point coproc */ |
#define | XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */ |
#define | XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */ |
#define | XINE_INT_TIMEOUT IP_LEV4 /* Timeout on I/O write */ |
#define | XINE_INT_TOY IP_LEV3 /* Clock chip */ |
#define | XINE_INT_1_10_MS IP_LEV2 /* Periodic interrupt */ |
#define | XINE_REG_CMR 0x0c000000 /* Color mask register */ |
#define | XINE_REG_MER 0x0c400000 /* Memory error register */ |
#define | XINE_REG_MSR 0x0c800000 /* Memory size register */ |
#define | XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */ |
#define | XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */ |
#define | XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */ |
#define | XINE_REG_AER 0x0e000004 /* Address error register */ |
#define | XINE_REG_TIMEOUT 0x0e00000c /* I/O write timeout reg */ |
#define | XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR ) |
#define | XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) |
#define | XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR ) |
#define | XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) |
#define | XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) |
#define | XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) |
#define | XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) |
#define | XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR ) |
#define | XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR ) |
#define | XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR ) |
#define | XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR ) |
#define | XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR ) |
#define | XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR ) |
#define | XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR ) |
#define | XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK ) |
#define | XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR ) |
#define | XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA ) |
#define | XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA ) |
#define | XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE ) |
#define | XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE ) |
#define | XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE ) |
#define | XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE ) |
#define | XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE ) |
#define | XINE_LANCE_CONFIG 3 |
#define | XINE_SCSI_CONFIG 14 |
#define | XINE_SCC0_CONFIG (0x10|4) |
#define | XINE_DTOP_CONFIG 10 |
#define | XINE_FLOPPY_CONFIG 13 |
#define | XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR ) |
#define | XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 ) |
#define | XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 ) |
#define | XINE_MER_xxx 0xf7fe30ff /* undefined */ |
#define | XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */ |
#define | XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ |
#define | XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */ |
#define | XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ |
#define | XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ |
#define | XINE_LASTB31 0x00000800 /* upper byte of word */ |
#define | XINE_LASTB23 0x00000400 /* .. through .. */ |
#define | XINE_LASTB15 0x00000200 /* .. the .. */ |
#define | XINE_LASTB07 0x00000100 /* .. lower byte */ |
#define | XINE_MSR_xxx 0xffffdfff /* undefined */ |
#define | XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */ |
#define | XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */ |
#define | XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */ |
#define | XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */ |
#define | XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */ |
#define | XINE_BANK_0 0x00020000 /* .. at bank 0, .. */ |
#define | XINE_BANK_1 0x00040000 /* .. at bank 1, .. */ |
#define | XINE_BANK_2 0x00080000 /* .. or at bank 2 */ |
#define | XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ |
#define | XINE_FI_VALUE 0x00001000 |
#define | XINE_CNFG_VALUE 121 |
#define | XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ |
#define | XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */ |
#define | XINE_CSR_DIAGDN 0x00008000 /* rw */ |
#define | XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */ |
#define | XINE_CSR_SCC_ENABLE 0x00000800 /* rw */ |
#define | XINE_CSR_RTC_ENABLE 0x00000400 /* rw */ |
#define | XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */ |
#define | XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */ |
#define | XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */ |
#define | XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */ |
#define | XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */ |
#define | XINE_CSR_LED 0x00000001 /* rw */ |
#define | XINE_INTR_xxxx 0x00002808 /* ro */ |
#define | XINE_INTR_FLOPPY 0x00008000 /* ro */ |
#define | XINE_INTR_NVR_JUMPER 0x00004000 /* ro */ |
#define | XINE_INTR_POWERUP 0x00002000 /* ro */ |
#define | XINE_INTR_TC_0 0x00001000 /* ro */ |
#define | XINE_INTR_ISDN 0x00000800 /* ro */ |
#define | XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
#define | XINE_INTR_SCSI 0x00000200 /* ro */ |
#define | XINE_INTR_LANCE 0x00000100 /* ro */ |
#define | XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */ |
#define | XINE_INTR_SCC_0 0x00000040 /* ro */ |
#define | XINE_INTR_TC_1 0x00000020 /* ro */ |
#define | XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */ |
#define | XINE_INTR_VINT 0x00000008 /* ro */ |
#define | XINE_INTR_N_VINT 0x00000004 /* ro */ |
#define | XINE_INTR_DTOP_TX 0x00000002 /* ro */ |
#define | XINE_INTR_DTOP_RX 0x00000001 /* ro */ |
#define | XINE_INTR_ASIC 0xffff0000 |
#define | XINE_INTR_DTOP 0x00000003 |
#define | XINE_IM0 0xffff9b6b /* all good ones enabled */ |
#define XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ |
Definition at line 266 of file dec_maxine.h.
#define XINE_BANK_0 0x00020000 /* .. at bank 0, .. */ |
Definition at line 236 of file dec_maxine.h.
#define XINE_BANK_1 0x00040000 /* .. at bank 1, .. */ |
Definition at line 237 of file dec_maxine.h.
#define XINE_BANK_2 0x00080000 /* .. or at bank 2 */ |
Definition at line 238 of file dec_maxine.h.
#define XINE_CNFG_VALUE 121 |
Definition at line 263 of file dec_maxine.h.
#define XINE_CSR_DIAGDN 0x00008000 /* rw */ |
Definition at line 276 of file dec_maxine.h.
#define XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */ |
Definition at line 284 of file dec_maxine.h.
#define XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */ |
Definition at line 282 of file dec_maxine.h.
#define XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */ |
Definition at line 277 of file dec_maxine.h.
#define XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */ |
Definition at line 281 of file dec_maxine.h.
#define XINE_CSR_LED 0x00000001 /* rw */ |
Definition at line 285 of file dec_maxine.h.
#define XINE_CSR_RTC_ENABLE 0x00000400 /* rw */ |
Definition at line 279 of file dec_maxine.h.
#define XINE_CSR_SCC_ENABLE 0x00000800 /* rw */ |
Definition at line 278 of file dec_maxine.h.
#define XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */ |
Definition at line 280 of file dec_maxine.h.
#define XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */ |
Definition at line 283 of file dec_maxine.h.
#define XINE_DTOP_CONFIG 10 |
Definition at line 207 of file dec_maxine.h.
#define XINE_FI_VALUE 0x00001000 |
Definition at line 242 of file dec_maxine.h.
#define XINE_FLOPPY_CONFIG 13 |
Definition at line 208 of file dec_maxine.h.
#define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR ) |
Definition at line 187 of file dec_maxine.h.
#define XINE_IM0 0xffff9b6b /* all good ones enabled */ |
Definition at line 308 of file dec_maxine.h.
Definition at line 165 of file dec_maxine.h.
#define XINE_INT_FPA IP_LEV7 /* Floating Point coproc */ |
Definition at line 160 of file dec_maxine.h.
#define XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */ |
Definition at line 161 of file dec_maxine.h.
#define XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */ |
Definition at line 162 of file dec_maxine.h.
Definition at line 163 of file dec_maxine.h.
#define XINE_INT_TOY IP_LEV3 /* Clock chip */ |
Definition at line 164 of file dec_maxine.h.
#define XINE_INTR_ASIC 0xffff0000 |
Definition at line 306 of file dec_maxine.h.
#define XINE_INTR_DTOP 0x00000003 |
Definition at line 307 of file dec_maxine.h.
#define XINE_INTR_DTOP_RX 0x00000001 /* ro */ |
Definition at line 305 of file dec_maxine.h.
#define XINE_INTR_DTOP_TX 0x00000002 /* ro */ |
Definition at line 304 of file dec_maxine.h.
#define XINE_INTR_FLOPPY 0x00008000 /* ro */ |
Definition at line 290 of file dec_maxine.h.
#define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */ |
Definition at line 298 of file dec_maxine.h.
#define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */ |
Definition at line 301 of file dec_maxine.h.
#define XINE_INTR_ISDN 0x00000800 /* ro */ |
Definition at line 294 of file dec_maxine.h.
#define XINE_INTR_LANCE 0x00000100 /* ro */ |
Definition at line 297 of file dec_maxine.h.
#define XINE_INTR_N_VINT 0x00000004 /* ro */ |
Definition at line 303 of file dec_maxine.h.
#define XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
Definition at line 295 of file dec_maxine.h.
#define XINE_INTR_NVR_JUMPER 0x00004000 /* ro */ |
Definition at line 291 of file dec_maxine.h.
#define XINE_INTR_POWERUP 0x00002000 /* ro */ |
Definition at line 292 of file dec_maxine.h.
#define XINE_INTR_SCC_0 0x00000040 /* ro */ |
Definition at line 299 of file dec_maxine.h.
#define XINE_INTR_SCSI 0x00000200 /* ro */ |
Definition at line 296 of file dec_maxine.h.
#define XINE_INTR_TC_0 0x00001000 /* ro */ |
Definition at line 293 of file dec_maxine.h.
#define XINE_INTR_TC_1 0x00000020 /* ro */ |
Definition at line 300 of file dec_maxine.h.
#define XINE_INTR_VINT 0x00000008 /* ro */ |
Definition at line 302 of file dec_maxine.h.
#define XINE_INTR_xxxx 0x00002808 /* ro */ |
Definition at line 289 of file dec_maxine.h.
#define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA ) |
Definition at line 197 of file dec_maxine.h.
#define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR ) |
Definition at line 190 of file dec_maxine.h.
#define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR ) |
Definition at line 191 of file dec_maxine.h.
#define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA ) |
Definition at line 196 of file dec_maxine.h.
#define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR ) |
Definition at line 188 of file dec_maxine.h.
#define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR ) |
Definition at line 189 of file dec_maxine.h.
#define XINE_LANCE_CONFIG 3 |
Definition at line 204 of file dec_maxine.h.
#define XINE_LASTB07 0x00000100 /* .. lower byte */ |
Definition at line 227 of file dec_maxine.h.
#define XINE_LASTB15 0x00000200 /* .. the .. */ |
Definition at line 226 of file dec_maxine.h.
#define XINE_LASTB23 0x00000400 /* .. through .. */ |
Definition at line 225 of file dec_maxine.h.
#define XINE_LASTB31 0x00000800 /* upper byte of word */ |
Definition at line 224 of file dec_maxine.h.
#define XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */ |
Definition at line 219 of file dec_maxine.h.
#define XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ |
Definition at line 223 of file dec_maxine.h.
#define XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ |
Definition at line 220 of file dec_maxine.h.
#define XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ |
Definition at line 222 of file dec_maxine.h.
#define XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */ |
Definition at line 221 of file dec_maxine.h.
#define XINE_MER_xxx 0xf7fe30ff /* undefined */ |
Definition at line 218 of file dec_maxine.h.
#define XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */ |
Definition at line 232 of file dec_maxine.h.
#define XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */ |
Definition at line 231 of file dec_maxine.h.
#define XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */ |
Definition at line 235 of file dec_maxine.h.
#define XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */ |
Definition at line 234 of file dec_maxine.h.
#define XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */ |
Definition at line 233 of file dec_maxine.h.
#define XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ |
Definition at line 239 of file dec_maxine.h.
#define XINE_MSR_xxx 0xffffdfff /* undefined */ |
Definition at line 230 of file dec_maxine.h.
#define XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */ |
Definition at line 110 of file dec_maxine.h.
#define XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */ |
Definition at line 109 of file dec_maxine.h.
#define XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ |
Definition at line 115 of file dec_maxine.h.
#define XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ |
Definition at line 114 of file dec_maxine.h.
#define XINE_PHYS_MAX 0x1fffffff |
Definition at line 98 of file dec_maxine.h.
#define XINE_PHYS_MEMORY_END |
Definition at line 104 of file dec_maxine.h.
#define XINE_PHYS_MEMORY_START 0x00000000 |
Definition at line 103 of file dec_maxine.h.
#define XINE_PHYS_MIN 0x00000000 /* 512 Meg */ |
Definition at line 97 of file dec_maxine.h.
#define XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ |
Definition at line 113 of file dec_maxine.h.
#define XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ |
Definition at line 112 of file dec_maxine.h.
#define XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ |
Definition at line 118 of file dec_maxine.h.
#define XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ |
Definition at line 117 of file dec_maxine.h.
#define XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ |
Definition at line 121 of file dec_maxine.h.
#define XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ |
Definition at line 120 of file dec_maxine.h.
#define XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ |
Definition at line 127 of file dec_maxine.h.
#define XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ |
Definition at line 126 of file dec_maxine.h.
#define XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */ |
Definition at line 130 of file dec_maxine.h.
#define XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */ |
Definition at line 123 of file dec_maxine.h.
#define XINE_PHYS_TC_START XINE_PHYS_TC_0_START |
Definition at line 129 of file dec_maxine.h.
#define XINE_REG_AER 0x0e000004 /* Address error register */ |
Definition at line 177 of file dec_maxine.h.
#define XINE_REG_CMR 0x0c000000 /* Color mask register */ |
Definition at line 170 of file dec_maxine.h.
#define XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */ |
Definition at line 176 of file dec_maxine.h.
#define XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR ) |
Definition at line 192 of file dec_maxine.h.
#define XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR ) |
Definition at line 195 of file dec_maxine.h.
#define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE ) |
Definition at line 202 of file dec_maxine.h.
#define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) |
Definition at line 186 of file dec_maxine.h.
#define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) |
Definition at line 185 of file dec_maxine.h.
#define XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */ |
Definition at line 173 of file dec_maxine.h.
#define XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */ |
Definition at line 174 of file dec_maxine.h.
#define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE ) |
Definition at line 203 of file dec_maxine.h.
#define XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK ) |
Definition at line 194 of file dec_maxine.h.
#define XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR ) |
Definition at line 193 of file dec_maxine.h.
#define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE ) |
Definition at line 199 of file dec_maxine.h.
#define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR ) |
Definition at line 182 of file dec_maxine.h.
#define XINE_REG_MER 0x0c400000 /* Memory error register */ |
Definition at line 171 of file dec_maxine.h.
#define XINE_REG_MSR 0x0c800000 /* Memory size register */ |
Definition at line 172 of file dec_maxine.h.
#define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE ) |
Definition at line 201 of file dec_maxine.h.
#define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) |
Definition at line 184 of file dec_maxine.h.
#define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) |
Definition at line 183 of file dec_maxine.h.
#define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE ) |
Definition at line 200 of file dec_maxine.h.
#define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) |
Definition at line 181 of file dec_maxine.h.
#define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR ) |
Definition at line 180 of file dec_maxine.h.
#define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR ) |
Definition at line 210 of file dec_maxine.h.
#define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 ) |
Definition at line 211 of file dec_maxine.h.
#define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 ) |
Definition at line 212 of file dec_maxine.h.
Definition at line 178 of file dec_maxine.h.
#define XINE_SCC0_CONFIG (0x10|4) |
Definition at line 206 of file dec_maxine.h.
#define XINE_SCSI_CONFIG 14 |
Definition at line 205 of file dec_maxine.h.
#define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) |
Definition at line 139 of file dec_maxine.h.
#define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START) |
Definition at line 141 of file dec_maxine.h.
#define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) |
Definition at line 155 of file dec_maxine.h.
#define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) |
Definition at line 154 of file dec_maxine.h.
#define XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START) |
Definition at line 147 of file dec_maxine.h.
#define XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START) |
Definition at line 149 of file dec_maxine.h.
#define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START) |
Definition at line 142 of file dec_maxine.h.
#define XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START) |
Definition at line 150 of file dec_maxine.h.
#define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START) |
Definition at line 152 of file dec_maxine.h.
#define XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START) |
Definition at line 148 of file dec_maxine.h.
#define XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START) |
Definition at line 143 of file dec_maxine.h.
#define XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START) |
Definition at line 140 of file dec_maxine.h.
#define XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START) |
Definition at line 144 of file dec_maxine.h.
#define XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START) |
Definition at line 151 of file dec_maxine.h.
#define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START) |
Definition at line 153 of file dec_maxine.h.
#define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START) |
Definition at line 145 of file dec_maxine.h.
#define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START) |
Definition at line 146 of file dec_maxine.h.
#define XINE_TC_MAX 1 /* only option slots */ |
Definition at line 134 of file dec_maxine.h.
#define XINE_TC_MIN 0 |
Definition at line 133 of file dec_maxine.h.
#define XINE_TC_NSLOTS 4 |
Definition at line 132 of file dec_maxine.h.
#define XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */ |
Definition at line 269 of file dec_maxine.h.