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#define | PSR_FLAGS 0xf0000000 /* flags */ |
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#define | PSR_N_bit (1 << 31) /* negative */ |
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#define | PSR_Z_bit (1 << 30) /* zero */ |
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#define | PSR_C_bit (1 << 29) /* carry */ |
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#define | PSR_V_bit (1 << 28) /* overflow */ |
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#define | PSR_Q_bit (1 << 27) /* saturation */ |
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#define | PSR_IT1_bit (1 << 26) |
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#define | PSR_IT0_bit (1 << 25) |
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#define | PSR_J_bit (1 << 24) /* Jazelle mode */ |
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#define | PSR_GE_bits (15 << 16) /* SIMD GE bits */ |
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#define | PSR_IT7_bit (1 << 15) |
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#define | PSR_IT6_bit (1 << 14) |
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#define | PSR_IT5_bit (1 << 13) |
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#define | PSR_IT4_bit (1 << 12) |
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#define | PSR_IT3_bit (1 << 11) |
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#define | PSR_IT2_bit (1 << 10) |
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#define | PSR_E_BIT (1 << 9) /* Endian state */ |
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#define | PSR_A_BIT (1 << 8) /* Async abort disable */ |
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#define | I32_bit (1 << 7) /* IRQ disable */ |
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#define | F32_bit (1 << 6) /* FIQ disable */ |
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#define | IF32_bits (3 << 6) /* IRQ/FIQ disable */ |
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#define | PSR_T_bit (1 << 5) /* Thumb state */ |
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#define | PSR_MODE 0x0000001f /* mode mask */ |
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#define | PSR_USR32_MODE 0x00000010 |
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#define | PSR_FIQ32_MODE 0x00000011 |
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#define | PSR_IRQ32_MODE 0x00000012 |
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#define | PSR_SVC32_MODE 0x00000013 |
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#define | PSR_MON32_MODE 0x00000016 |
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#define | PSR_ABT32_MODE 0x00000017 |
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#define | PSR_HYP32_MODE 0x0000001a |
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#define | PSR_UND32_MODE 0x0000001b |
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#define | PSR_SYS32_MODE 0x0000001f |
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#define | PSR_32_MODE 0x00000010 |
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#define | R15_FLAGS 0xf0000000 |
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#define | R15_FLAG_N 0x80000000 |
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#define | R15_FLAG_Z 0x40000000 |
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#define | R15_FLAG_C 0x20000000 |
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#define | R15_FLAG_V 0x10000000 |
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#define | ARM_CP15_CPU_ID 0 |
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#define | ARM_ISA3_SYNCHPRIM_MASK 0x0000f000 |
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#define | ARM_ISA4_SYNCHPRIM_MASK 0x00f00000 |
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#define | ARM_ISA3_SYNCHPRIM_LDREX 0x10 |
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#define | ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 |
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#define | ARM_ISA3_SYNCHPRIM_LDREXD 0x20 |
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#define | ARM_PFR0_THUMBEE_MASK 0x0000f000 |
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#define | ARM_PFR1_GTIMER_MASK 0x000f0000 |
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#define | ARM_PFR1_VIRT_MASK 0x0000f000 |
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#define | ARM_PFR1_SEC_MASK 0x000000f0 |
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#define | ARM_MVFR0_ROUNDING_MASK 0xf0000000 |
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#define | ARM_MVFR0_SHORTVEC_MASK 0x0f000000 |
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#define | ARM_MVFR0_SQRT_MASK 0x00f00000 |
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#define | ARM_MVFR0_DIVIDE_MASK 0x000f0000 |
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#define | ARM_MVFR0_EXCEPT_MASK 0x0000f000 |
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#define | ARM_MVFR0_DFLOAT_MASK 0x00000f00 |
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#define | ARM_MVFR0_SFLOAT_MASK 0x000000f0 |
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#define | ARM_MVFR0_ASIMD_MASK 0x0000000f |
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#define | ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 |
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#define | ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 |
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#define | ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 |
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#define | ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 |
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#define | ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 |
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#define | ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 |
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#define | ARM_MVFR1_D_NAN_MASK 0x000000f0 |
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#define | ARM_MVFR1_FTZ_MASK 0x0000000f |
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#define | ARM3_CP15_FLUSH 1 |
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#define | ARM3_CP15_CONTROL 2 |
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#define | ARM3_CP15_CACHEABLE 3 |
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#define | ARM3_CP15_UPDATEABLE 4 |
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#define | ARM3_CP15_DISRUPTIVE 5 |
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#define | ARM3_CTL_CACHE_ON 0x00000001 |
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#define | ARM3_CTL_SHARED 0x00000002 |
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#define | ARM3_CTL_MONITOR 0x00000004 |
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#define | CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ |
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#define | CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ |
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#define | CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ |
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#define | CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ |
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#define | CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ |
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#define | CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ |
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#define | CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ |
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#define | CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ |
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#define | CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ |
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#define | CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ |
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#define | CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ |
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#define | CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ |
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#define | CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ |
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#define | CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ |
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#define | CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ |
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#define | CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ |
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#define | CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ |
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#define | CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */ |
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#define | CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */ |
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#define | CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */ |
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#define | CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ |
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#define | CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ |
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#define | CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ |
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#define | CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ |
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#define | CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ |
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#define | CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ |
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#define | CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ |
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#define | CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ |
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#define | CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ |
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#define | CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE |
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#define | CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ |
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#define | CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ |
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#define | CPACR_CPn(n) (3 << (2*n)) |
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#define | CPACR_NOACCESS 0 /* reset value */ |
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#define | CPACR_PRIVED 1 /* Privileged mode access */ |
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#define | CPACR_RESERVED 2 |
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#define | CPACR_ALL 3 /* Privileged and User mode access */ |
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#define | NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */ |
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#define | NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */ |
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#define | NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */ |
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#define | NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */ |
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#define | NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */ |
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#define | ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ |
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#define | ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ |
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#define | ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ |
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#define | ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ |
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#define | ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ |
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#define | ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ |
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#define | ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ |
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#define | ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ |
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#define | ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ |
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#define | ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ |
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#define | ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ |
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#define | ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ |
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#define | ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ |
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#define | XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ |
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#define | XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ |
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#define | XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ |
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#define | XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ |
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#define | XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ |
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#define | XSCALE_AUXCTL_MD_MASK 0x00000030 |
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#define | MPCORE_AUXCTL_RS 0x00000001 /* return stack */ |
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#define | MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ |
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#define | MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ |
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#define | MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ |
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#define | MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ |
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#define | MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ |
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#define | PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */ |
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#define | PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */ |
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#define | PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */ |
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#define | PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */ |
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#define | PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */ |
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#define | PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */ |
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#define | PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */ |
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#define | PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/ |
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#define | CORTEXA5_ACTLR_FW __BIT(0) |
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#define | CORTEXA5_ACTLR_SMP __BIT(6) /* Inner Cache Shared is cacheable */ |
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#define | CORTEXA5_ACTLR_EXCL __BIT(7) /* Exclusive L1/L2 cache control */ |
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#define | CORTEXA7_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */ |
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#define | CORTEXA7_ACTLR_L2EN __BIT(1) /* Enables L2 cache */ |
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#define | CORTEXA7_ACTLR_SMP __BIT(6) /* SMP */ |
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#define | CORTEXA8_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */ |
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#define | CORTEXA8_ACTLR_L2EN __BIT(1) /* Enables L2 cache */ |
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#define | CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ |
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#define | CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */ |
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#define | CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */ |
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#define | CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ |
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#define | CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ |
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#define | CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ |
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#define | CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ |
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#define | CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ |
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#define | CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */ |
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#define | CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */ |
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#define | CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */ |
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#define | CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */ |
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#define | FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ |
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#define | FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ |
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#define | FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ |
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#define | FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ |
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#define | FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ |
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#define | FC_L2CACHE_EN 0x00400000 /* L2 enable */ |
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#define | FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ |
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#define | FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ |
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#define | FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ |
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#define | FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ |
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#define | CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ |
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#define | CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ |
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#define | CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ |
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#define | CPU_CT_S (1U << 24) /* split cache */ |
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#define | CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ |
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#define | CPU_CT_CTYPE_WT 0 /* write-through */ |
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#define | CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ |
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#define | CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ |
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#define | CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ |
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#define | CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ |
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#define | CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ |
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#define | CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ |
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#define | CPU_CT_xSIZE_M (1U << 2) /* multiplier */ |
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#define | CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ |
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#define | CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ |
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#define | CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ |
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#define | CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ |
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#define | CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ |
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#define | CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ |
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#define | CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ |
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#define | CPU_CT4_L1_VIPT 2 /* VIPT */ |
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#define | CPU_CT4_L1_PIPT 3 /* PIPT */ |
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#define | CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ |
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#define | CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ |
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#define | CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ |
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#define | CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ |
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#define | CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ |
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#define | CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ |
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#define | CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) |
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#define | CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) |
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#define | CPU_CSID_LEN(x) ((x) & 0x07) |
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#define | CPU_CSSR_L2 0x00000002 |
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#define | CPU_CSSR_L1 0x00000000 |
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#define | CPU_CSSR_InD 0x00000001 |
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#define | FAULT_TYPE_MASK 0x0f |
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#define | FAULT_USER 0x10 |
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#define | FAULT_WRTBUF_0 0x00 /* Vector Exception */ |
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#define | FAULT_WRTBUF_1 0x02 /* Terminal Exception */ |
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#define | FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ |
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#define | FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ |
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#define | FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ |
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#define | FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ |
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#define | FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ |
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#define | FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ |
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#define | FAULT_ALIGN_0 0x01 /* Alignment */ |
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#define | FAULT_ALIGN_1 0x03 /* Alignment */ |
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#define | FAULT_TRANS_S 0x05 /* Translation -- Section */ |
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#define | FAULT_TRANS_P 0x07 /* Translation -- Page */ |
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#define | FAULT_DOMAIN_S 0x09 /* Domain -- Section */ |
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#define | FAULT_DOMAIN_P 0x0b /* Domain -- Page */ |
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#define | FAULT_PERM_S 0x0d /* Permission -- Section */ |
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#define | FAULT_PERM_P 0x0f /* Permission -- Page */ |
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#define | FAULT_LPAE 0x0200 /* (SW) used long descriptors */ |
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#define | FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */ |
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#define | FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */ |
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#define | FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */ |
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#define | FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */ |
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#define | ARM_VECTORS_LOW 0x00000000U |
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#define | ARM_VECTORS_HIGH 0xffff0000U |
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#define | INSN_SIZE 4 /* Always 4 bytes */ |
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#define | INSN_COND_MASK 0xf0000000 /* Condition mask */ |
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#define | INSN_COND_EQ 0 /* Z == 1 */ |
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#define | INSN_COND_NE 1 /* Z == 0 */ |
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#define | INSN_COND_CS 2 /* C == 1 */ |
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#define | INSN_COND_CC 3 /* C == 0 */ |
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#define | INSN_COND_MI 4 /* N == 1 */ |
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#define | INSN_COND_PL 5 /* N == 0 */ |
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#define | INSN_COND_VS 6 /* V == 1 */ |
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#define | INSN_COND_VC 7 /* V == 0 */ |
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#define | INSN_COND_HI 8 /* C == 1 && Z == 0 */ |
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#define | INSN_COND_LS 9 /* C == 0 || Z == 1 */ |
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#define | INSN_COND_GE 10 /* N == V */ |
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#define | INSN_COND_LT 11 /* N != V */ |
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#define | INSN_COND_GT 12 /* Z == 0 && N == V */ |
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#define | INSN_COND_LE 13 /* Z == 1 || N != V */ |
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#define | INSN_COND_AL 14 /* Always condition */ |
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#define | THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ |
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#define | ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ |
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#define | ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ |
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#define | ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ |
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#define | ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ |
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#define | ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ |
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#define | ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ |
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#define | ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ |
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#define | ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ |
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#define | ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ |
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#define | ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ |
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#define | ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ |
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#define | ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ |
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#define | ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ |
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#define | ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ |
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#define | ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ |
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#define | ARM11_PMCCTL_SBZ (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) |
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#define | ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ |
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#define | ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ |
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#define | ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ |
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#define | ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ |
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#define | ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ |
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#define | ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ |
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#define | ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ |
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#define | ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ |
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#define | ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ |
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#define | ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ |
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#define | ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ |
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#define | ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ |
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#define | ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ |
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#define | ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ |
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#define | ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ |
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#define | ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ |
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#define | ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ |
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#define | ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ |
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#define | ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ |
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#define | ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ |
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#define | ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ |
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#define | ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ |
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#define | ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ |
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#define | ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ |
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#define | CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ |
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#define | CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ |
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#define | CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ |
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#define | L2CTRL_NUMCPU __BITS(25,24) |
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#define | L2CTRL_ICPRES __BIT(23) |
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#define | TTBR_C __BIT(0) /* without MPE */ |
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#define | TTBR_S __BIT(1) |
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#define | TTBR_IMP __BIT(2) |
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#define | TTBR_RGN_MASK __BITS(4,3) |
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#define | TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK) |
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#define | TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK) |
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#define | TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK) |
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#define | TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK) |
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#define | TTBR_NOS __BIT(5) |
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#define | TTBR_IRGN_MASK (__BIT(6) | __BIT(0)) |
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#define | TTBR_IRGN_NC 0 |
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#define | TTBR_IRGN_WBWA __BIT(6) |
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#define | TTBR_IRGN_WT __BIT(0) |
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#define | TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6)) |
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#define | TTBCR_S_EAE __BIT(31) |
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#define | TTBCR_S_PD1 __BIT(5) |
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#define | TTBCR_S_PD0 __BIT(4) |
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#define | TTBCR_S_N __BITS(2,0) |
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#define | TTBCR_L_EAE __BIT(31) |
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#define | TTBCR_L_SH1 __BITS(29,28) |
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#define | TTBCR_L_ORGN1 __BITS(27,26) |
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#define | TTBCR_L_IRGN1 __BITS(25,24) |
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#define | TTBCR_L_EPD1 __BIT(23) |
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#define | TTBCR_L_A1 __BIT(22) |
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#define | TTBCR_L_T1SZ __BITS(18,16) |
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#define | TTBCR_L_SH0 __BITS(13,12) |
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#define | TTBCR_L_ORGN0 __BITS(11,10) |
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#define | TTBCR_L_IRGN0 __BITS(9,8) |
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#define | TTBCR_L_EPD0 __BIT(7) |
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#define | TTBCR_L_T0SZ __BITS(2,0) |
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#define | NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) |
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#define | NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) |
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#define | NRRR_NC 0 |
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#define | NRRR_WB_WA 1 |
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#define | NRRR_WT 2 |
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#define | NRRR_WB 3 |
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#define | PRRR_NOSn(n) __BITS(24+2*(n)) |
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#define | PRRR_NS1 __BIT(19) |
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#define | PRRR_NS0 __BIT(18) |
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#define | PRRR_DS1 __BIT(17) |
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#define | PRRR_DS0 __BIT(16) |
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#define | PRRR_TRn(n) __BITS(1+2*(n),0+2*(n)) |
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#define | PRRR_TR_STRONG 0 |
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#define | PRRR_TR_DEVICE 1 |
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#define | PRRR_TR_NORMAL 2 |
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#define | MPIDR_MP __BIT(31) /* 1 = Have MP Extention */ |
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#define | MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ |
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#define | MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ |
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#define | MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ |
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#define | MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ |
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#define | MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ |
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#define | CORTEXA9_MPIDR_MP MPIDR_MP |
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#define | CORTEXA9_MPIDR_U MPIDR_U |
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#define | CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ |
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#define | CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */ |
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#define | PJ4B_MPIDR_MP MPIDR_MP |
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#define | PJ4B_MPIDR_U MPIDR_U |
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#define | PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */ |
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#define | PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ |
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#define | PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */ |
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#define | CNTCTL_ISTATUS __BIT(2) |
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#define | CNTCTL_IMASK __BIT(1) |
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#define | CNTCTL_ENABLE __BIT(0) |
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#define | CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */ |
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#define | CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */ |
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#define | CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */ |
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#define | CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */ |
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#define | CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */ |
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#define | CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */ |
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#define | CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */ |
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#define | CNTHCTL_EVNTI __BITS(7,4) |
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#define | CNTHCTL_EVNTDIR __BIT(3) |
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#define | CNTHCTL_EVNTEN __BIT(2) |
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#define | CNTHCTL_PL1PCEN __BIT(1) |
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#define | CNTHCTL_PL1PCTEN __BIT(0) |
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#define | ARM_A5_TLBDATA_DOM __BITS(62,59) |
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#define | ARM_A5_TLBDATA_AP __BITS(58,56) |
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#define | ARM_A5_TLBDATA_NS_WALK __BIT(55) |
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#define | ARM_A5_TLBDATA_NS_PAGE __BIT(54) |
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#define | ARM_A5_TLBDATA_XN __BIT(53) |
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#define | ARM_A5_TLBDATA_TEX __BITS(52,50) |
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#define | ARM_A5_TLBDATA_B __BIT(49) |
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#define | ARM_A5_TLBDATA_C __BIT(48) |
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#define | ARM_A5_TLBDATA_S __BIT(47) |
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#define | ARM_A5_TLBDATA_ASID __BITS(46,39) |
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#define | ARM_A5_TLBDATA_SIZE __BITS(38,37) |
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#define | ARM_A5_TLBDATA_SIZE_4KB 0 |
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#define | ARM_A5_TLBDATA_SIZE_16KB 1 |
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#define | ARM_A5_TLBDATA_SIZE_1MB 2 |
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#define | ARM_A5_TLBDATA_SIZE_16MB 3 |
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#define | ARM_A5_TLBDATA_VA __BITS(36,22) |
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#define | ARM_A5_TLBDATA_PA __BITS(21,2) |
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#define | ARM_A5_TLBDATA_nG __BIT(1) |
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#define | ARM_A5_TLBDATA_VALID __BIT(0) |
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#define | ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64) |
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#define | ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64) |
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#define | ARM_A7_TLBDATA2_S1_SIZE_4KB 0 |
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#define | ARM_A7_TLBDATA2_S1_SIZE_64KB 1 |
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#define | ARM_A7_TLBDATA2_S1_SIZE_1MB 2 |
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#define | ARM_A7_TLBDATA2_S1_SIZE_16MB 3 |
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#define | ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64) |
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#define | ARM_A7_TLBDATA2_IS __BITS(77-64,76-64) |
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#define | ARM_A7_TLBDATA2_IS_NC 0 |
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#define | ARM_A7_TLBDATA2_IS_WB_WA 1 |
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#define | ARM_A7_TLBDATA2_IS_WT 2 |
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#define | ARM_A7_TLBDATA2_IS_DSO 3 |
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#define | ARM_A7_TLBDATA2_S2OVR __BIT(75-64) |
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#define | ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64) |
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#define | ARM_A7_TLBDATA2_SDO_MT_D 2 |
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#define | ARM_A7_TLBDATA2_SDO_MT_SO 6 |
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#define | ARM_A7_TLBDATA2_OS __BITS(75-64,74-64) |
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#define | ARM_A7_TLBDATA2_OS_NC 0 |
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#define | ARM_A7_TLBDATA2_OS_WB_WA 1 |
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#define | ARM_A7_TLBDATA2_OS_WT 2 |
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#define | ARM_A7_TLBDATA2_OS_WB 3 |
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#define | ARM_A7_TLBDATA2_SH __BITS(73-64,72-64) |
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#define | ARM_A7_TLBDATA2_SH_NONE 0 |
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#define | ARM_A7_TLBDATA2_SH_UNUSED 1 |
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#define | ARM_A7_TLBDATA2_SH_OS 2 |
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#define | ARM_A7_TLBDATA2_SH_IS 3 |
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#define | ARM_A7_TLBDATA2_XN2 __BIT(71-64) |
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#define | ARM_A7_TLBDATA2_XN1 __BIT(70-64) |
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#define | ARM_A7_TLBDATA2_PXN __BIT(69-64) |
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#define | ARM_A7_TLBDATA12_PA __BITS(68-32,41-32) |
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#define | ARM_A7_TLBDATA1_NS __BIT(40-32) |
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#define | ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32) |
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#define | ARM_A7_TLBDATA1_AP __BITS(37-32,35-32) |
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#define | ARM_A7_TLBDATA1_nG __BIT(34-32) |
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#define | ARM_A7_TLBDATA01_ASID __BITS(33,26) |
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#define | ARM_A7_TLBDATA0_VMID __BITS(25,18) |
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#define | ARM_A7_TLBDATA0_VA __BITS(17,5) |
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#define | ARM_A7_TLBDATA0_NS_WALK __BIT(4) |
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#define | ARM_A7_TLBDATA0_SIZE __BITS(3,1) |
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#define | ARM_A7_TLBDATA0_SIZE_V7_4KB 0 |
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#define | ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1 |
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#define | ARM_A7_TLBDATA0_SIZE_V7_64KB 2 |
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#define | ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3 |
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#define | ARM_A7_TLBDATA0_SIZE_V7_1MB 4 |
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#define | ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5 |
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#define | ARM_A7_TLBDATA0_SIZE_V7_16MB 6 |
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#define | ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7 |
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#define | ARM_TLBDATA_VALID __BIT(0) |
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#define | ARM_TLBDATAOP_WAY __BIT(31) |
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#define | ARM_A5_TLBDATAOP_INDEX __BITS(5,0) |
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#define | ARM_A7_TLBDATAOP_INDEX __BITS(6,0) |
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#define | ARMREG_READ_INLINE(name, __insnstring) |
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#define | ARMREG_WRITE_INLINE(name, __insnstring) |
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#define | ARMREG_READ_INLINE2(name, __insnstring) |
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#define | ARMREG_WRITE_INLINE2(name, __insnstring) |
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#define | ARMREG_READ64_INLINE(name, __insnstring) |
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#define | ARMREG_WRITE64_INLINE(name, __insnstring) |
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| ARMREG_READ_INLINE2 (fpsid, "vmrs\t%0, fpsid") ARMREG_READ_INLINE2(fpscr |
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vmrs fpscr | ARMREG_WRITE_INLINE2 (fpscr, "vmsr\tfpscr, %0") ARMREG_READ_INLINE2(mvfr1 |
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vmrs fpscr vmrs mvfr1 | ARMREG_READ_INLINE2 (mvfr0, "vmrs\t%0, mvfr0") ARMREG_READ_INLINE2(fpexc |
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vmrs fpscr vmrs mvfr1 vmrs fpexc | ARMREG_WRITE_INLINE2 (fpexc, "vmsr\tfpexc, %0") ARMREG_READ_INLINE2(fpinst |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst | ARMREG_WRITE_INLINE2 (fpinst, "fmxr\tfpinst, %0") ARMREG_READ_INLINE2(fpinst2 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE2 (fpinst2, "fmxr\tfpinst2, %0") ARMREG_READ_INLINE(midr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (ctr, "p15,0,%0,c0,c0,1") ARMREG_READ_INLINE(tlbtr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (mpidr, "p15,0,%0,c0,c0,5") ARMREG_READ_INLINE(revidr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (pfr0, "p15,0,%0,c0,c1,0") ARMREG_READ_INLINE(pfr1 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (mmfr0, "p15,0,%0,c0,c1,4") ARMREG_READ_INLINE(mmfr1 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (mmfr2, "p15,0,%0,c0,c1,6") ARMREG_READ_INLINE(mmfr3 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (isar0, "p15,0,%0,c0,c2,0") ARMREG_READ_INLINE(isar1 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (isar2, "p15,0,%0,c0,c2,2") ARMREG_READ_INLINE(isar3 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (isar4, "p15,0,%0,c0,c2,4") ARMREG_READ_INLINE(isar5 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (ccsidr, "p15,1,%0,c0,c0,0") ARMREG_READ_INLINE(clidr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (csselr, "p15,2,%0,c0,c0,0") ARMREG_WRITE_INLINE(csselr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (sctlr, "p15,0,%0,c1,c0,0") ARMREG_WRITE_INLINE(sctlr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (auxctl, "p15,0,%0,c1,c0,1") ARMREG_WRITE_INLINE(auxctl |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cpacr, "p15,0,%0,c1,c0,2") ARMREG_WRITE_INLINE(cpacr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (scr, "p15,0,%0,c1,c1,0") ARMREG_READ_INLINE(nsacr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (ttbr, "p15,0,%0,c2,c0,0") ARMREG_WRITE_INLINE(ttbr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (ttbr1, "p15,0,%0,c2,c0,1") ARMREG_WRITE_INLINE(ttbr1 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (ttbcr, "p15,0,%0,c2,c0,2") ARMREG_WRITE_INLINE(ttbcr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (dacr, "p15,0,%0,c3,c0,0") ARMREG_WRITE_INLINE(dacr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (dfsr, "p15,0,%0,c5,c0,0") ARMREG_READ_INLINE(ifsr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (dfar, "p15,0,%0,c6,c0,0") ARMREG_READ_INLINE(ifar |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (icialluis, "p15,0,%0,c7,c1,0") ARMREG_WRITE_INLINE(bpiallis |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (par, "p15,0,%0,c7,c4,0") ARMREG_WRITE_INLINE(iciallu |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (icimvau, "p15,0,%0,c7,c5,1") ARMREG_WRITE_INLINE(isb |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (bpiall, "p15,0,%0,c7,c5,6") ARMREG_WRITE_INLINE(bpimva |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dcimvac, "p15,0,%0,c7,c6,1") ARMREG_WRITE_INLINE(dcisw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (ats1cpr, "p15,0,%0,c7,c8,0") ARMREG_WRITE_INLINE(ats1cpw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (ats1cur, "p15,0,%0,c7,c8,2") ARMREG_WRITE_INLINE(ats1cuw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dccmvac, "p15,0,%0,c7,c10,1") ARMREG_WRITE_INLINE(dccsw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dsb, "p15,0,%0,c7,c10,4") ARMREG_WRITE_INLINE(dmb |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dccmvau, "p15,0,%0,c7,c11,1") ARMREG_WRITE_INLINE(dccimvac |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dccisw, "p15,0,%0,c7,c14,2") ARMREG_WRITE_INLINE(tlbiallis |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (tlbimvais, "p15,0,%0,c8,c3,1") ARMREG_WRITE_INLINE(tlbiasidis |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (tlbimvaais, "p15,0,%0,c8,c3,3") ARMREG_WRITE_INLINE(itlbiall |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (itlbimva, "p15,0,%0,c8,c5,1") ARMREG_WRITE_INLINE(itlbiasid |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dtlbiall, "p15,0,%0,c8,c6,0") ARMREG_WRITE_INLINE(dtlbimva |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (dtlbiasid, "p15,0,%0,c8,c6,2") ARMREG_WRITE_INLINE(tlbiall |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (tlbimva, "p15,0,%0,c8,c7,1") ARMREG_WRITE_INLINE(tlbiasid |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (tlbimvaa, "p15,0,%0,c8,c7,3") ARMREG_READ_INLINE(pmcr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmcr, "p15,0,%0,c9,c12,0") ARMREG_READ_INLINE(pmcntenset |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmcntenset, "p15,0,%0,c9,c12,1") ARMREG_READ_INLINE(pmcntenclr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmcntenclr, "p15,0,%0,c9,c12,2") ARMREG_READ_INLINE(pmovsr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmovsr, "p15,0,%0,c9,c12,3") ARMREG_READ_INLINE(pmselr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmselr, "p15,0,%0,c9,c12,5") ARMREG_READ_INLINE(pmceid0 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (pmceid1, "p15,0,%0,c9,c12,7") ARMREG_READ_INLINE(pmccntr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmccntr, "p15,0,%0,c9,c13,0") ARMREG_READ_INLINE(pmxevtyper |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmxevtyper, "p15,0,%0,c9,c13,1") ARMREG_READ_INLINE(pmxevcntr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmxevcntr, "p15,0,%0,c9,c13,2") ARMREG_READ_INLINE(pmuserenr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmuserenr, "p15,0,%0,c9,c14,0") ARMREG_READ_INLINE(pmintenset |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmintenset, "p15,0,%0,c9,c14,1") ARMREG_READ_INLINE(pmintenclr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_WRITE_INLINE (pmintenclr, "p15,0,%0,c9,c14,2") ARMREG_READ_INLINE(l2ctrl |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (prrr, "p15,0,%0,c10,c2,0") ARMREG_WRITE_INLINE(prrr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (nrrr, "p15,0,%0,c10,c2,1") ARMREG_WRITE_INLINE(nrrr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (contextidr, "p15,0,%0,c13,c0,1") ARMREG_WRITE_INLINE(contextidr |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (tpidrurw, "p15,0,%0,c13,c0,2") ARMREG_WRITE_INLINE(tpidrurw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (tpidruro, "p15,0,%0,c13,c0,3") ARMREG_WRITE_INLINE(tpidruro |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (tpidrprw, "p15,0,%0,c13,c0,4") ARMREG_WRITE_INLINE(tpidrprw |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (vbar, "p15,0,%0,c12,c0,0") ARMREG_WRITE_INLINE(vbar |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cnt_frq, "p15,0,%0,c14,c0,0") ARMREG_WRITE_INLINE(cnt_frq |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cntk_ctl, "p15,0,%0,c14,c1,0") ARMREG_WRITE_INLINE(cntk_ctl |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cntp_tval, "p15,0,%0,c14,c2,0") ARMREG_WRITE_INLINE(cntp_tval |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cntp_ctl, "p15,0,%0,c14,c2,1") ARMREG_WRITE_INLINE(cntp_ctl |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cntv_tval, "p15,0,%0,c14,c3,0") ARMREG_WRITE_INLINE(cntv_tval |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ_INLINE (cntv_ctl, "p15,0,%0,c14,c3,1") ARMREG_WRITE_INLINE(cntv_ctl |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 | ARMREG_READ64_INLINE (cntp_ct, "p15,0,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntp_ct |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 | ARMREG_READ64_INLINE (cntv_ct, "p15,1,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntv_ct |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 | ARMREG_READ64_INLINE (cntp_cval, "p15,2,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntp_cval |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 | ARMREG_READ64_INLINE (cntv_cval, "p15,3,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntv_cval |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 | ARMREG_READ64_INLINE (cntvoff, "p15,4,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntvoff |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 | ARMREG_READ_INLINE (cbar, "p15,4,%0,c15,c0,0") ARMREG_READ_INLINE(pmcrv6 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 | ARMREG_WRITE_INLINE (pmcrv6, "p15,0,%0,c15,c12,0") ARMREG_READ_INLINE(pmccntrv6 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 | ARMREG_WRITE_INLINE (pmccntrv6, "p15,0,%0,c15,c12,1") ARMREG_READ_INLINE(tlbdata0 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 | ARMREG_READ_INLINE (tlbdata1, "p15,3,%0,c15,c0,1") ARMREG_READ_INLINE(tlbdata2 |
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 | ARMREG_WRITE_INLINE (tlbdataop, "p15,3,%0,c15,c4,2") ARMREG_READ_INLINE(sheeva_xctrl |
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