sh4_pcicreg.h File Reference

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Macros
sh4_pcicreg.h File Reference

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Macros

#define SH4_PCIC   0xfe200000
 
#define SH4_PCIC_IO   0xfe240000
 
#define SH4_PCIC_IO_SIZE   0x00040000
 
#define SH4_PCIC_IO_MASK   (SH4_PCIC_IO_SIZE-1)
 
#define SH4_PCIC_MEM   0xfd000000
 
#define SH4_PCIC_MEM_SIZE   0x01000000
 
#define SH4_PCIC_MEM_MASK   (SH4_PCIC_MEM_SIZE-1)
 
#define SH4_PCICONF   (SH4_PCIC+0x000) /* 32bit */
 
#define SH4_PCICONF0   (SH4_PCICONF+0x00) /* 32bit */
 
#define SH4_PCICONF1   (SH4_PCICONF+0x04) /* 32bit */
 
#define SH4_PCICONF2   (SH4_PCICONF+0x08) /* 32bit */
 
#define SH4_PCICONF3   (SH4_PCICONF+0x0c) /* 32bit */
 
#define SH4_PCICONF4   (SH4_PCICONF+0x10) /* 32bit */
 
#define SH4_PCICONF5   (SH4_PCICONF+0x14) /* 32bit */
 
#define SH4_PCICONF6   (SH4_PCICONF+0x18) /* 32bit */
 
#define SH4_PCICONF7   (SH4_PCICONF+0x1c) /* 32bit */
 
#define SH4_PCICONF8   (SH4_PCICONF+0x20) /* 32bit */
 
#define SH4_PCICONF9   (SH4_PCICONF+0x24) /* 32bit */
 
#define SH4_PCICONF10   (SH4_PCICONF+0x28) /* 32bit */
 
#define SH4_PCICONF11   (SH4_PCICONF+0x2c) /* 32bit */
 
#define SH4_PCICONF12   (SH4_PCICONF+0x30) /* 32bit */
 
#define SH4_PCICONF13   (SH4_PCICONF+0x34) /* 32bit */
 
#define SH4_PCICONF14   (SH4_PCICONF+0x38) /* 32bit */
 
#define SH4_PCICONF15   (SH4_PCICONF+0x3c) /* 32bit */
 
#define SH4_PCICONF16   (SH4_PCICONF+0x40) /* 32bit */
 
#define SH4_PCICONF17   (SH4_PCICONF+0x44) /* 32bit */
 
#define SH4_PCICR   (SH4_PCIC+0x100) /* 32bit */
 
#define SH4_PCILSR0   (SH4_PCIC+0x104) /* 32bit */
 
#define SH4_PCILSR1   (SH4_PCIC+0x108) /* 32bit */
 
#define SH4_PCILAR0   (SH4_PCIC+0x10c) /* 32bit */
 
#define SH4_PCILAR1   (SH4_PCIC+0x110) /* 32bit */
 
#define SH4_PCIINT   (SH4_PCIC+0x114) /* 32bit */
 
#define SH4_PCIINTM   (SH4_PCIC+0x118) /* 32bit */
 
#define SH4_PCIALR   (SH4_PCIC+0x11c) /* 32bit */
 
#define SH4_PCICLR   (SH4_PCIC+0x120) /* 32bit */
 
#define SH4_PCIAINT   (SH4_PCIC+0x130) /* 32bit */
 
#define SH4_PCIAINTM   (SH4_PCIC+0x134) /* 32bit */
 
#define SH4_PCIDMABT   (SH4_PCIC+0x140) /* 32bit */
 
#define SH4_PCIDPA0   (SH4_PCIC+0x180) /* 32bit */
 
#define SH4_PCIDLA0   (SH4_PCIC+0x184) /* 32bit */
 
#define SH4_PCIDTC0   (SH4_PCIC+0x188) /* 32bit */
 
#define SH4_PCIDCR0   (SH4_PCIC+0x18c) /* 32bit */
 
#define SH4_PCIDPA1   (SH4_PCIC+0x190) /* 32bit */
 
#define SH4_PCIDLA1   (SH4_PCIC+0x194) /* 32bit */
 
#define SH4_PCIDTC1   (SH4_PCIC+0x198) /* 32bit */
 
#define SH4_PCIDCR1   (SH4_PCIC+0x19c) /* 32bit */
 
#define SH4_PCIDPA2   (SH4_PCIC+0x1a0) /* 32bit */
 
#define SH4_PCIDLA2   (SH4_PCIC+0x1a4) /* 32bit */
 
#define SH4_PCIDTC2   (SH4_PCIC+0x1a8) /* 32bit */
 
#define SH4_PCIDCR2   (SH4_PCIC+0x1ac) /* 32bit */
 
#define SH4_PCIDPA3   (SH4_PCIC+0x1b0) /* 32bit */
 
#define SH4_PCIDLA3   (SH4_PCIC+0x1b4) /* 32bit */
 
#define SH4_PCIDTC3   (SH4_PCIC+0x1b8) /* 32bit */
 
#define SH4_PCIDCR3   (SH4_PCIC+0x1bc) /* 32bit */
 
#define SH4_PCIPAR   (SH4_PCIC+0x1c0) /* 32bit */
 
#define SH4_PCIMBR   (SH4_PCIC+0x1c4) /* 32bit */
 
#define SH4_PCIIOBR   (SH4_PCIC+0x1c8) /* 32bit */
 
#define SH4_PCIPINT   (SH4_PCIC+0x1cc) /* 32bit */
 
#define SH4_PCIPINTM   (SH4_PCIC+0x1d0) /* 32bit */
 
#define SH4_PCICLKR   (SH4_PCIC+0x1d4) /* 32bit */
 
#define SH4_PCIBCR1   (SH4_PCIC+0x1e0) /* 32bit */
 
#define SH4_PCIBCR2   (SH4_PCIC+0x1e4) /* 32bit */
 
#define SH4_PCIWCR1   (SH4_PCIC+0x1e8) /* 32bit */
 
#define SH4_PCIWCR2   (SH4_PCIC+0x1ec) /* 32bit */
 
#define SH4_PCIWCR3   (SH4_PCIC+0x1f0) /* 32bit */
 
#define SH4_PCIMCR   (SH4_PCIC+0x1f4) /* 32bit */
 
#define SH4_PCIBCR3   (SH4_PCIC+0x1f8) /* 32bit: SH7751R */
 
#define SH4_PCIPCTR   (SH4_PCIC+0x200) /* 32bit */
 
#define SH4_PCIPDTR   (SH4_PCIC+0x204) /* 32bit */
 
#define SH4_PCIPDR   (SH4_PCIC+0x220) /* 32bit */
 
#define PCICR_BASE   0xa5000000
 
#define PCICR_TRDSGL   0x00000200
 
#define PCICR_BYTESWAP   0x00000100
 
#define PCICR_PCIPUP   0x00000080
 
#define PCICR_BMABT   0x00000040
 
#define PCICR_MD10   0x00000020
 
#define PCICR_MD9   0x00000010
 
#define PCICR_SERR   0x00000008
 
#define PCICR_INTA   0x00000004
 
#define PCICR_RSTCTL   0x00000002
 
#define PCICR_CFINIT   0x00000001
 
#define PCIINT_M_LOCKON   0x00008000
 
#define PCIINT_T_TGT_ABORT   0x00004000
 
#define PCIINT_TGT_RETRY   0x00000200
 
#define PCIINT_MST_DIS   0x00000100
 
#define PCIINT_ADRPERR   0x00000080
 
#define PCIINT_SERR_DET   0x00000040
 
#define PCIINT_T_DPERR_WT   0x00000020
 
#define PCIINT_T_PERR_DET   0x00000010
 
#define PCIINT_M_TGT_ABORT   0x00000008
 
#define PCIINT_M_MST_ABORT   0x00000004
 
#define PCIINT_M_DPERR_WT   0x00000002
 
#define PCIINT_M_DPERR_RD   0x00000001
 
#define PCIINT_ALL   0x0000c3ff
 
#define PCIINT_CLEAR_ALL   PCIINT_ALL
 
#define PCIINTM_MASK_ALL   0x00000000
 
#define PCIINTM_UNMASK_ALL   PCIINT_ALL
 
#define PCIMBR_MASK   0xff000000
 
#define PCIIOBR_MASK   0xffc00000
 

Macro Definition Documentation

◆ PCICR_BASE

#define PCICR_BASE   0xa5000000

Definition at line 112 of file sh4_pcicreg.h.

◆ PCICR_BMABT

#define PCICR_BMABT   0x00000040

Definition at line 116 of file sh4_pcicreg.h.

◆ PCICR_BYTESWAP

#define PCICR_BYTESWAP   0x00000100

Definition at line 114 of file sh4_pcicreg.h.

◆ PCICR_CFINIT

#define PCICR_CFINIT   0x00000001

Definition at line 122 of file sh4_pcicreg.h.

◆ PCICR_INTA

#define PCICR_INTA   0x00000004

Definition at line 120 of file sh4_pcicreg.h.

◆ PCICR_MD10

#define PCICR_MD10   0x00000020

Definition at line 117 of file sh4_pcicreg.h.

◆ PCICR_MD9

#define PCICR_MD9   0x00000010

Definition at line 118 of file sh4_pcicreg.h.

◆ PCICR_PCIPUP

#define PCICR_PCIPUP   0x00000080

Definition at line 115 of file sh4_pcicreg.h.

◆ PCICR_RSTCTL

#define PCICR_RSTCTL   0x00000002

Definition at line 121 of file sh4_pcicreg.h.

◆ PCICR_SERR

#define PCICR_SERR   0x00000008

Definition at line 119 of file sh4_pcicreg.h.

◆ PCICR_TRDSGL

#define PCICR_TRDSGL   0x00000200

Definition at line 113 of file sh4_pcicreg.h.

◆ PCIINT_ADRPERR

#define PCIINT_ADRPERR   0x00000080

Definition at line 128 of file sh4_pcicreg.h.

◆ PCIINT_ALL

#define PCIINT_ALL   0x0000c3ff

Definition at line 136 of file sh4_pcicreg.h.

◆ PCIINT_CLEAR_ALL

#define PCIINT_CLEAR_ALL   PCIINT_ALL

Definition at line 137 of file sh4_pcicreg.h.

◆ PCIINT_M_DPERR_RD

#define PCIINT_M_DPERR_RD   0x00000001

Definition at line 135 of file sh4_pcicreg.h.

◆ PCIINT_M_DPERR_WT

#define PCIINT_M_DPERR_WT   0x00000002

Definition at line 134 of file sh4_pcicreg.h.

◆ PCIINT_M_LOCKON

#define PCIINT_M_LOCKON   0x00008000

Definition at line 124 of file sh4_pcicreg.h.

◆ PCIINT_M_MST_ABORT

#define PCIINT_M_MST_ABORT   0x00000004

Definition at line 133 of file sh4_pcicreg.h.

◆ PCIINT_M_TGT_ABORT

#define PCIINT_M_TGT_ABORT   0x00000008

Definition at line 132 of file sh4_pcicreg.h.

◆ PCIINT_MST_DIS

#define PCIINT_MST_DIS   0x00000100

Definition at line 127 of file sh4_pcicreg.h.

◆ PCIINT_SERR_DET

#define PCIINT_SERR_DET   0x00000040

Definition at line 129 of file sh4_pcicreg.h.

◆ PCIINT_T_DPERR_WT

#define PCIINT_T_DPERR_WT   0x00000020

Definition at line 130 of file sh4_pcicreg.h.

◆ PCIINT_T_PERR_DET

#define PCIINT_T_PERR_DET   0x00000010

Definition at line 131 of file sh4_pcicreg.h.

◆ PCIINT_T_TGT_ABORT

#define PCIINT_T_TGT_ABORT   0x00004000

Definition at line 125 of file sh4_pcicreg.h.

◆ PCIINT_TGT_RETRY

#define PCIINT_TGT_RETRY   0x00000200

Definition at line 126 of file sh4_pcicreg.h.

◆ PCIINTM_MASK_ALL

#define PCIINTM_MASK_ALL   0x00000000

Definition at line 139 of file sh4_pcicreg.h.

◆ PCIINTM_UNMASK_ALL

#define PCIINTM_UNMASK_ALL   PCIINT_ALL

Definition at line 140 of file sh4_pcicreg.h.

◆ PCIIOBR_MASK

#define PCIIOBR_MASK   0xffc00000

Definition at line 144 of file sh4_pcicreg.h.

◆ PCIMBR_MASK

#define PCIMBR_MASK   0xff000000

Definition at line 142 of file sh4_pcicreg.h.

◆ SH4_PCIAINT

#define SH4_PCIAINT   (SH4_PCIC+0x130) /* 32bit */

Definition at line 76 of file sh4_pcicreg.h.

◆ SH4_PCIAINTM

#define SH4_PCIAINTM   (SH4_PCIC+0x134) /* 32bit */

Definition at line 77 of file sh4_pcicreg.h.

◆ SH4_PCIALR

#define SH4_PCIALR   (SH4_PCIC+0x11c) /* 32bit */

Definition at line 74 of file sh4_pcicreg.h.

◆ SH4_PCIBCR1

#define SH4_PCIBCR1   (SH4_PCIC+0x1e0) /* 32bit */

Definition at line 101 of file sh4_pcicreg.h.

◆ SH4_PCIBCR2

#define SH4_PCIBCR2   (SH4_PCIC+0x1e4) /* 32bit */

Definition at line 102 of file sh4_pcicreg.h.

◆ SH4_PCIBCR3

#define SH4_PCIBCR3   (SH4_PCIC+0x1f8) /* 32bit: SH7751R */

Definition at line 107 of file sh4_pcicreg.h.

◆ SH4_PCIC

#define SH4_PCIC   0xfe200000

Definition at line 39 of file sh4_pcicreg.h.

◆ SH4_PCIC_IO

#define SH4_PCIC_IO   0xfe240000

Definition at line 41 of file sh4_pcicreg.h.

◆ SH4_PCIC_IO_MASK

#define SH4_PCIC_IO_MASK   (SH4_PCIC_IO_SIZE-1)

Definition at line 43 of file sh4_pcicreg.h.

◆ SH4_PCIC_IO_SIZE

#define SH4_PCIC_IO_SIZE   0x00040000

Definition at line 42 of file sh4_pcicreg.h.

◆ SH4_PCIC_MEM

#define SH4_PCIC_MEM   0xfd000000

Definition at line 44 of file sh4_pcicreg.h.

◆ SH4_PCIC_MEM_MASK

#define SH4_PCIC_MEM_MASK   (SH4_PCIC_MEM_SIZE-1)

Definition at line 46 of file sh4_pcicreg.h.

◆ SH4_PCIC_MEM_SIZE

#define SH4_PCIC_MEM_SIZE   0x01000000

Definition at line 45 of file sh4_pcicreg.h.

◆ SH4_PCICLKR

#define SH4_PCICLKR   (SH4_PCIC+0x1d4) /* 32bit */

Definition at line 100 of file sh4_pcicreg.h.

◆ SH4_PCICLR

#define SH4_PCICLR   (SH4_PCIC+0x120) /* 32bit */

Definition at line 75 of file sh4_pcicreg.h.

◆ SH4_PCICONF

#define SH4_PCICONF   (SH4_PCIC+0x000) /* 32bit */

Definition at line 48 of file sh4_pcicreg.h.

◆ SH4_PCICONF0

#define SH4_PCICONF0   (SH4_PCICONF+0x00) /* 32bit */

Definition at line 49 of file sh4_pcicreg.h.

◆ SH4_PCICONF1

#define SH4_PCICONF1   (SH4_PCICONF+0x04) /* 32bit */

Definition at line 50 of file sh4_pcicreg.h.

◆ SH4_PCICONF10

#define SH4_PCICONF10   (SH4_PCICONF+0x28) /* 32bit */

Definition at line 59 of file sh4_pcicreg.h.

◆ SH4_PCICONF11

#define SH4_PCICONF11   (SH4_PCICONF+0x2c) /* 32bit */

Definition at line 60 of file sh4_pcicreg.h.

◆ SH4_PCICONF12

#define SH4_PCICONF12   (SH4_PCICONF+0x30) /* 32bit */

Definition at line 61 of file sh4_pcicreg.h.

◆ SH4_PCICONF13

#define SH4_PCICONF13   (SH4_PCICONF+0x34) /* 32bit */

Definition at line 62 of file sh4_pcicreg.h.

◆ SH4_PCICONF14

#define SH4_PCICONF14   (SH4_PCICONF+0x38) /* 32bit */

Definition at line 63 of file sh4_pcicreg.h.

◆ SH4_PCICONF15

#define SH4_PCICONF15   (SH4_PCICONF+0x3c) /* 32bit */

Definition at line 64 of file sh4_pcicreg.h.

◆ SH4_PCICONF16

#define SH4_PCICONF16   (SH4_PCICONF+0x40) /* 32bit */

Definition at line 65 of file sh4_pcicreg.h.

◆ SH4_PCICONF17

#define SH4_PCICONF17   (SH4_PCICONF+0x44) /* 32bit */

Definition at line 66 of file sh4_pcicreg.h.

◆ SH4_PCICONF2

#define SH4_PCICONF2   (SH4_PCICONF+0x08) /* 32bit */

Definition at line 51 of file sh4_pcicreg.h.

◆ SH4_PCICONF3

#define SH4_PCICONF3   (SH4_PCICONF+0x0c) /* 32bit */

Definition at line 52 of file sh4_pcicreg.h.

◆ SH4_PCICONF4

#define SH4_PCICONF4   (SH4_PCICONF+0x10) /* 32bit */

Definition at line 53 of file sh4_pcicreg.h.

◆ SH4_PCICONF5

#define SH4_PCICONF5   (SH4_PCICONF+0x14) /* 32bit */

Definition at line 54 of file sh4_pcicreg.h.

◆ SH4_PCICONF6

#define SH4_PCICONF6   (SH4_PCICONF+0x18) /* 32bit */

Definition at line 55 of file sh4_pcicreg.h.

◆ SH4_PCICONF7

#define SH4_PCICONF7   (SH4_PCICONF+0x1c) /* 32bit */

Definition at line 56 of file sh4_pcicreg.h.

◆ SH4_PCICONF8

#define SH4_PCICONF8   (SH4_PCICONF+0x20) /* 32bit */

Definition at line 57 of file sh4_pcicreg.h.

◆ SH4_PCICONF9

#define SH4_PCICONF9   (SH4_PCICONF+0x24) /* 32bit */

Definition at line 58 of file sh4_pcicreg.h.

◆ SH4_PCICR

#define SH4_PCICR   (SH4_PCIC+0x100) /* 32bit */

Definition at line 67 of file sh4_pcicreg.h.

◆ SH4_PCIDCR0

#define SH4_PCIDCR0   (SH4_PCIC+0x18c) /* 32bit */

Definition at line 82 of file sh4_pcicreg.h.

◆ SH4_PCIDCR1

#define SH4_PCIDCR1   (SH4_PCIC+0x19c) /* 32bit */

Definition at line 86 of file sh4_pcicreg.h.

◆ SH4_PCIDCR2

#define SH4_PCIDCR2   (SH4_PCIC+0x1ac) /* 32bit */

Definition at line 90 of file sh4_pcicreg.h.

◆ SH4_PCIDCR3

#define SH4_PCIDCR3   (SH4_PCIC+0x1bc) /* 32bit */

Definition at line 94 of file sh4_pcicreg.h.

◆ SH4_PCIDLA0

#define SH4_PCIDLA0   (SH4_PCIC+0x184) /* 32bit */

Definition at line 80 of file sh4_pcicreg.h.

◆ SH4_PCIDLA1

#define SH4_PCIDLA1   (SH4_PCIC+0x194) /* 32bit */

Definition at line 84 of file sh4_pcicreg.h.

◆ SH4_PCIDLA2

#define SH4_PCIDLA2   (SH4_PCIC+0x1a4) /* 32bit */

Definition at line 88 of file sh4_pcicreg.h.

◆ SH4_PCIDLA3

#define SH4_PCIDLA3   (SH4_PCIC+0x1b4) /* 32bit */

Definition at line 92 of file sh4_pcicreg.h.

◆ SH4_PCIDMABT

#define SH4_PCIDMABT   (SH4_PCIC+0x140) /* 32bit */

Definition at line 78 of file sh4_pcicreg.h.

◆ SH4_PCIDPA0

#define SH4_PCIDPA0   (SH4_PCIC+0x180) /* 32bit */

Definition at line 79 of file sh4_pcicreg.h.

◆ SH4_PCIDPA1

#define SH4_PCIDPA1   (SH4_PCIC+0x190) /* 32bit */

Definition at line 83 of file sh4_pcicreg.h.

◆ SH4_PCIDPA2

#define SH4_PCIDPA2   (SH4_PCIC+0x1a0) /* 32bit */

Definition at line 87 of file sh4_pcicreg.h.

◆ SH4_PCIDPA3

#define SH4_PCIDPA3   (SH4_PCIC+0x1b0) /* 32bit */

Definition at line 91 of file sh4_pcicreg.h.

◆ SH4_PCIDTC0

#define SH4_PCIDTC0   (SH4_PCIC+0x188) /* 32bit */

Definition at line 81 of file sh4_pcicreg.h.

◆ SH4_PCIDTC1

#define SH4_PCIDTC1   (SH4_PCIC+0x198) /* 32bit */

Definition at line 85 of file sh4_pcicreg.h.

◆ SH4_PCIDTC2

#define SH4_PCIDTC2   (SH4_PCIC+0x1a8) /* 32bit */

Definition at line 89 of file sh4_pcicreg.h.

◆ SH4_PCIDTC3

#define SH4_PCIDTC3   (SH4_PCIC+0x1b8) /* 32bit */

Definition at line 93 of file sh4_pcicreg.h.

◆ SH4_PCIINT

#define SH4_PCIINT   (SH4_PCIC+0x114) /* 32bit */

Definition at line 72 of file sh4_pcicreg.h.

◆ SH4_PCIINTM

#define SH4_PCIINTM   (SH4_PCIC+0x118) /* 32bit */

Definition at line 73 of file sh4_pcicreg.h.

◆ SH4_PCIIOBR

#define SH4_PCIIOBR   (SH4_PCIC+0x1c8) /* 32bit */

Definition at line 97 of file sh4_pcicreg.h.

◆ SH4_PCILAR0

#define SH4_PCILAR0   (SH4_PCIC+0x10c) /* 32bit */

Definition at line 70 of file sh4_pcicreg.h.

◆ SH4_PCILAR1

#define SH4_PCILAR1   (SH4_PCIC+0x110) /* 32bit */

Definition at line 71 of file sh4_pcicreg.h.

◆ SH4_PCILSR0

#define SH4_PCILSR0   (SH4_PCIC+0x104) /* 32bit */

Definition at line 68 of file sh4_pcicreg.h.

◆ SH4_PCILSR1

#define SH4_PCILSR1   (SH4_PCIC+0x108) /* 32bit */

Definition at line 69 of file sh4_pcicreg.h.

◆ SH4_PCIMBR

#define SH4_PCIMBR   (SH4_PCIC+0x1c4) /* 32bit */

Definition at line 96 of file sh4_pcicreg.h.

◆ SH4_PCIMCR

#define SH4_PCIMCR   (SH4_PCIC+0x1f4) /* 32bit */

Definition at line 106 of file sh4_pcicreg.h.

◆ SH4_PCIPAR

#define SH4_PCIPAR   (SH4_PCIC+0x1c0) /* 32bit */

Definition at line 95 of file sh4_pcicreg.h.

◆ SH4_PCIPCTR

#define SH4_PCIPCTR   (SH4_PCIC+0x200) /* 32bit */

Definition at line 108 of file sh4_pcicreg.h.

◆ SH4_PCIPDR

#define SH4_PCIPDR   (SH4_PCIC+0x220) /* 32bit */

Definition at line 110 of file sh4_pcicreg.h.

◆ SH4_PCIPDTR

#define SH4_PCIPDTR   (SH4_PCIC+0x204) /* 32bit */

Definition at line 109 of file sh4_pcicreg.h.

◆ SH4_PCIPINT

#define SH4_PCIPINT   (SH4_PCIC+0x1cc) /* 32bit */

Definition at line 98 of file sh4_pcicreg.h.

◆ SH4_PCIPINTM

#define SH4_PCIPINTM   (SH4_PCIC+0x1d0) /* 32bit */

Definition at line 99 of file sh4_pcicreg.h.

◆ SH4_PCIWCR1

#define SH4_PCIWCR1   (SH4_PCIC+0x1e8) /* 32bit */

Definition at line 103 of file sh4_pcicreg.h.

◆ SH4_PCIWCR2

#define SH4_PCIWCR2   (SH4_PCIC+0x1ec) /* 32bit */

Definition at line 104 of file sh4_pcicreg.h.

◆ SH4_PCIWCR3

#define SH4_PCIWCR3   (SH4_PCIC+0x1f0) /* 32bit */

Definition at line 105 of file sh4_pcicreg.h.


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