cpu_alpha_instr_loadstore.cc Source File

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cpu_alpha_instr_loadstore.cc
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1 /*
2  * Copyright (C) 2005-2018 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * Alpha load/store instructions. (Included from cpu_alpha_instr_inc.c.)
29  *
30  *
31  * Load/store instructions have the following arguments:
32  *
33  * arg[0] = pointer to the register to load to or store from (uint64_t)
34  * arg[1] = pointer to the base register (uint64_t)
35  * arg[2] = offset (as an int32_t)
36  *
37  * NOTE:
38  * Alpha byte and word loads (8- and 16-bit) are unsigned, while
39  * 32-bit long words are sign-extended up to 64 bits during a load!
40  */
41 
42 
43 #ifndef LS_IGNORE_OFFSET
44 static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
45 {
46 #ifdef LS_B
47  unsigned char data[1];
48 #endif
49 #ifdef LS_W
50  unsigned char data[2];
51 #endif
52 #ifdef LS_L
53  unsigned char data[4];
54 #endif
55 #ifdef LS_Q
56  unsigned char data[8];
57 #endif
58  uint64_t addr = *((uint64_t *)ic->arg[1]);
59  uint64_t data_x;
60 
61  addr += (int32_t)ic->arg[2];
62 #ifdef LS_UNALIGNED
63  addr &= ~7;
64 #endif
65 
66 #ifdef LS_LOAD
67  /* Load: */
68  if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
69  MEM_READ, CACHE_DATA)) {
70  fatal("store failed: TODO\n");
71  exit(1);
72  }
73 
74  data_x = data[0];
75 #ifndef LS_B
76  data_x += (data[1] << 8);
77 #ifndef LS_W
78  data_x += (data[2] << 16);
79  data_x += ((uint64_t)data[3] << 24);
80 #ifdef LS_L
81  data_x = (int64_t)(int32_t)data_x;
82 #endif
83 #ifndef LS_L
84  data_x += ((uint64_t)data[4] << 32);
85  data_x += ((uint64_t)data[5] << 40);
86  data_x += ((uint64_t)data[6] << 48);
87  data_x += ((uint64_t)data[7] << 56);
88 #endif
89 #endif
90 #endif
91  *((uint64_t *)ic->arg[0]) = data_x;
92 #else
93  /* Store: */
94  data_x = *((uint64_t *)ic->arg[0]);
95  data[0] = data_x;
96 #ifndef LS_B
97  data[1] = data_x >> 8;
98 #ifndef LS_W
99  data[2] = data_x >> 16;
100  data[3] = data_x >> 24;
101 #ifndef LS_L
102  data[4] = data_x >> 32;
103  data[5] = data_x >> 40;
104  data[6] = data_x >> 48;
105  data[7] = data_x >> 56;
106 #endif
107 #endif
108 #endif
109 
110  if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
111  MEM_WRITE, CACHE_DATA)) {
112  fatal("store failed: TODO\n");
113  exit(1);
114  }
115 
116 #ifdef LS_LLSC
117 #ifndef LS_LOAD
118  *((uint64_t *)ic->arg[0]) = 1;
119 #endif
120 #endif
121 
122 #endif
123 }
124 #endif
125 
126 
127 static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
128 {
129  unsigned char *page;
130  uint64_t addr = (*((uint64_t *)ic->arg[1]))
131 #ifndef LS_IGNORE_OFFSET
132  + (int32_t)ic->arg[2]
133 #endif
134  ;
135 
136  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
137  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
138  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
139  uint32_t x1, x2, x3, c;
140  struct DYNTRANS_L2_64_TABLE *l2;
141  struct DYNTRANS_L3_64_TABLE *l3;
142  x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
143  x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
144  x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
145  /* fatal("X3: addr=%016" PRIx64" x1=%x x2=%x x3=%x\n",
146  (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
147  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
148  /* fatal(" l2 = %p\n", l2); */
149  l3 = l2->l3[x2];
150  /* fatal(" l3 = %p\n", l3); */
151 #ifdef LS_LOAD
152  page = l3->host_load[x3];
153 #else
154  page = l3->host_store[x3];
155 #endif
156 
157 #ifdef LS_UNALIGNED
158  addr &= ~7;
159 #endif
160 
161 #ifdef LS_LLSC
162 #ifdef LS_LOAD
163  /* TODO: cache-line size! */
164  cpu->cd.alpha.load_linked_addr = addr & ~63;
165  cpu->cd.alpha.ll_flag = 1;
166 #else
167  /* TODO: only invalidate per cache line, not everything! */
168  if (cpu->cd.alpha.ll_flag == 1) {
169  int i;
170  for (i=0; i<cpu->machine->ncpus; i++)
171  cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
172  } else {
173  *((uint64_t *)ic->arg[0]) = 0;
174  return;
175  }
176 #endif
177 #endif
178 
179  c = addr & 8191;
180 
181 #ifndef LS_B
182  if (c &
183 #ifdef LS_W
184  1
185 #endif
186 #ifdef LS_L
187  3
188 #endif
189 #ifdef LS_Q
190  7
191 #endif
192  ) {
193  LS_GENERIC_N(cpu, ic);
194  return;
195  }
196  else
197 #endif
198 
199  if (page != NULL) {
200 #ifdef LS_LOAD
201 #ifdef HOST_BIG_ENDIAN
202  uint64_t data_x;
203  data_x = page[c];
204 #ifndef LS_B
205  data_x += (page[c+1] << 8);
206 #ifndef LS_W
207  data_x += (page[c+2] << 16);
208  data_x += ((uint64_t)page[c+3] << 24);
209 #ifndef LS_L
210  data_x += ((uint64_t)page[c+4] << 32);
211  data_x += ((uint64_t)page[c+5] << 40);
212  data_x += ((uint64_t)page[c+6] << 48);
213  data_x += ((uint64_t)page[c+7] << 56);
214 #endif
215 #endif
216 #endif
217 #ifdef LS_L
218  *((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
219 #else
220  *((uint64_t *)ic->arg[0]) = data_x;
221 #endif
222 #else
223 #ifdef LS_B
224  *((uint64_t *)ic->arg[0]) = page[c];
225 #endif
226 #ifdef LS_W
227  uint16_t d = *((uint16_t *) (page + c));
228  *((uint64_t *)ic->arg[0]) = d;
229 #endif
230 #ifdef LS_L
231  int32_t d = *((int32_t *) (page + c));
232  *((uint64_t *)ic->arg[0]) = (int64_t)d;
233 #endif
234 #ifdef LS_Q
235  uint64_t d = *((uint64_t *) (page + c));
236  *((uint64_t *)ic->arg[0]) = d;
237 #endif
238 #endif
239 #else
240  /* Store: */
241 #ifdef HOST_BIG_ENDIAN
242  uint64_t data_x = *((uint64_t *)ic->arg[0]);
243  page[c] = data_x;
244 #ifndef LS_B
245  page[c+1] = data_x >> 8;
246 #ifndef LS_W
247  page[c+2] = data_x >> 16;
248  page[c+3] = data_x >> 24;
249 #ifndef LS_L
250  page[c+4] = data_x >> 32;
251  page[c+5] = data_x >> 40;
252  page[c+6] = data_x >> 48;
253  page[c+7] = data_x >> 56;
254 #endif
255 #endif
256 #endif
257 #else
258  /* Native byte order: */
259 #ifdef LS_B
260  page[c] = *((uint64_t *)ic->arg[0]);
261 #endif
262 #ifdef LS_W
263  uint32_t d = *((uint64_t *)ic->arg[0]);
264  *((uint16_t *) (page + c)) = d;
265 #endif
266 #ifdef LS_L
267  uint32_t d = *((uint64_t *)ic->arg[0]);
268  *((uint32_t *) (page + c)) = d;
269 #endif
270 #ifdef LS_Q
271  uint64_t d = *((uint64_t *)ic->arg[0]);
272  *((uint64_t *) (page + c)) = d;
273 #endif
274 #endif
275 
276 #ifdef LS_LLSC
277 #ifndef LS_LOAD
278  *((uint64_t *)ic->arg[0]) = 1;
279 #endif
280 #endif
281 
282 #endif /* !LS_LOAD */
283  } else
284  LS_GENERIC_N(cpu, ic);
285 }
286 
data
u_short data
Definition: siireg.h:79
machine::cpus
struct cpu ** cpus
Definition: machine.h:140
LS_IGNORE_OFFSET
#define LS_IGNORE_OFFSET
Definition: tmp_alpha_misc.cc:1133
if
addr & if(addr >=0x24 &&page !=NULL)
Definition: tmp_arm_multi.cc:56
DYNTRANS_L1N
#define DYNTRANS_L1N
Definition: cpu.h:222
cpu::alpha
struct alpha_cpu alpha
Definition: cpu.h:440
MEM_READ
#define MEM_READ
Definition: memory.h:116
addr
uint32_t addr
Definition: tmp_arm_multi.cc:52
MEM_WRITE
#define MEM_WRITE
Definition: memory.h:117
LS_GENERIC_N
void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic)
Definition: cpu_ppc_instr_loadstore.cc:42
LS_LOAD
#define LS_LOAD
Definition: tmp_alpha_misc.cc:1154
fatal
void fatal(const char *fmt,...)
Definition: main.cc:152
cpu::cd
union cpu::@1 cd
page
page
Definition: tmp_arm_multi.cc:54
ic
struct arm_instr_call * ic
Definition: tmp_arm_multi.cc:50
CACHE_DATA
#define CACHE_DATA
Definition: memory.h:121
LS_UNALIGNED
#define LS_UNALIGNED
Definition: tmp_alpha_misc.cc:1146
DYNTRANS_L2N
#define DYNTRANS_L2N
Definition: tmp_alpha_head.cc:10
cpu::mem
struct memory * mem
Definition: cpu.h:362
DYNTRANS_L3N
#define DYNTRANS_L3N
Definition: tmp_alpha_head.cc:11
cpu::machine
struct machine * machine
Definition: cpu.h:328
alpha_cpu::ll_flag
int ll_flag
Definition: cpu_alpha.h:159
DYNTRANS_L3_64_TABLE
#define DYNTRANS_L3_64_TABLE
Definition: tmp_alpha_head.cc:16
LS_W
#define LS_W
Definition: tmp_alpha_misc.cc:1027
LS_N
#define LS_N
Definition: tmp_alpha_misc.cc:1157
LS_L
#define LS_L
Definition: tmp_alpha_misc.cc:1123
cpu
Definition: cpu.h:326
DYNTRANS_L2_64_TABLE
#define DYNTRANS_L2_64_TABLE
Definition: tmp_alpha_head.cc:15
cpu::memory_rw
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
Definition: cpu.h:365
alpha_cpu::load_linked_addr
uint64_t load_linked_addr
Definition: cpu_alpha.h:158
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#define LS_Q
Definition: tmp_alpha_misc.cc:1155
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int ncpus
Definition: machine.h:139

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