sh4_scifreg.h File Reference

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sh4_scifreg.h File Reference

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Macros

#define SH3_SCIF0_BASE   0xa4000150
 
#define SH3_SCIF1_BASE   0xa4000140
 
#define SH4_SCIF_BASE   0xffe80000
 
#define SCIF_SMR   0x00 /* serial mode */
 
#define SCIF_BRR   0x04 /* bit rate */
 
#define SCIF_SCR   0x08 /* serial control */
 
#define SCIF_FTDR   0x0c /* transmit fifo data */
 
#define SCIF_SSR   0x10 /* serial status */
 
#define SCIF_FRDR   0x14 /* receive fifo data */
 
#define SCIF_FCR   0x18 /* fifo control */
 
#define SCIF_FDR   0x1c /* fifo data count set */
 
#define SCIF_SPTR   0x20 /* serial port */
 
#define SCIF_LSR   0x24 /* line status */
 
#define SHREG_SCSMR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
 
#define SHREG_SCBRR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_BRR))
 
#define SHREG_SCSCR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
 
#define SHREG_SCFTDR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FTDR))
 
#define SHREG_SCSSR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
 
#define SHREG_SCFRDR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FRDR))
 
#define SHREG_SCFCR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
 
#define SHREG_SCFDR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))
 
#define SHREG_SCSPTR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
 
#define SHREG_SCLSR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))
 
#define SHREG_SCSFDR2   SHREG_SCFTDR2
 
#define SHREG_SCFSR2   SHREG_SCSSR2
 
#define SCSPTR2_RTSIO   0x0080
 
#define SCSPTR2_RTSDT   0x0040
 
#define SCSPTR2_CTSIO   0x0020
 
#define SCSPTR2_CTSDT   0x0010
 
#define SCSPTR2_SCKIO   0x0008
 
#define SCSPTR2_SCKDT   0x0004
 
#define SCSPTR2_SPB2IO   0x0002
 
#define SCSPTR2_SPB2DT   0x0001
 
#define SCLSR2_ORER   0x0001 /* overrun error */
 
#define SCSMR2_CHR   0x40 /* character width (set = 7bit) */
 
#define SCSMR2_PE   0x20 /* Parity Enable */
 
#define SCSMR2_O   0x10 /* parity mode Odd */
 
#define SCSMR2_STOP   0x08 /* STOP bit (set = 2 stop bits) */
 
#define SCSMR2_CKS1   0x02 /* ClocK Select 1 */
 
#define SCSMR2_CKS0   0x01 /* ClocK Select 0 */
 
#define SCSMR2_IRMOD   0x80 /* IrDA mode */
 
#define SCSMR2_ICK3   0x40
 
#define SCSMR2_ICK2   0x20
 
#define SCSMR2_ICK1   0x10
 
#define SCSMR2_ICK0   0x08
 
#define SCSMR2_PSEL   0x04 /* Pulse width SELelect */
 
#define SCSCR2_TIE   0x80 /* Transmit Interrupt Enable */
 
#define SCSCR2_RIE   0x40 /* Recieve Interrupt Enable */
 
#define SCSCR2_TE   0x20 /* Transmit Enable */
 
#define SCSCR2_RE   0x10 /* Receive Enable */
 
#define SCSCR2_CKE1   0x02 /* ClocK Enable 1 */
 
#define SCSCR2_CKE0   0x01 /* ClocK Enable 0 (not in sh4) */
 
#define SCSSR2_ER   0x0080 /* ERror */
 
#define SCSSR2_TEND   0x0040 /* Transmit END */
 
#define SCSSR2_TDFE   0x0020 /* Transmit Data Fifo Empty */
 
#define SCSSR2_BRK   0x0010 /* BReaK detection */
 
#define SCSSR2_FER   0x0008 /* Framing ERror */
 
#define SCSSR2_PER   0x0004 /* Parity ERror */
 
#define SCSSR2_RDF   0x0002 /* Recieve fifo Data Full */
 
#define SCSSR2_DR   0x0001 /* Data Ready */
 
#define SCFCR2_RTRG1   0x80 /* Receive TRiGger 1 */
 
#define SCFCR2_RTRG0   0x40 /* Receive TRiGger 0 */
 
#define SCFCR2_TTRG1   0x20 /* Transmit TRiGger 1 */
 
#define SCFCR2_TTRG0   0x10 /* Transmit TRiGger 0 */
 
#define SCFCR2_MCE   0x08 /* Modem Control Enable */
 
#define SCFCR2_TFRST   0x04 /* Transmit Fifo register ReSeT */
 
#define SCFCR2_RFRST   0x02 /* Receive Fifo register ReSeT */
 
#define SCFCR2_LOOP   0x01 /* LOOP back test */
 
#define FIFO_RCV_TRIGGER_1   0x00
 
#define FIFO_RCV_TRIGGER_4   0x40
 
#define FIFO_RCV_TRIGGER_8   0x80
 
#define FIFO_RCV_TRIGGER_14   0xc0
 
#define FIFO_XMT_TRIGGER_8   0x00
 
#define FIFO_XMT_TRIGGER_4   0x10
 
#define FIFO_XMT_TRIGGER_2   0x20
 
#define FIFO_XMT_TRIGGER_1   0x30
 
#define SCFDR2_TXCNT   0xff00 /* Tx CouNT */
 
#define SCFDR2_RECVCNT   0x00ff /* Rx CouNT */
 
#define SCFDR2_TXF_FULL   0x1000 /* Tx FULL */
 
#define SCFDR2_RXF_EPTY   0x0000 /* Rx EMPTY */
 

Macro Definition Documentation

◆ FIFO_RCV_TRIGGER_1

#define FIFO_RCV_TRIGGER_1   0x00

Definition at line 152 of file sh4_scifreg.h.

◆ FIFO_RCV_TRIGGER_14

#define FIFO_RCV_TRIGGER_14   0xc0

Definition at line 155 of file sh4_scifreg.h.

◆ FIFO_RCV_TRIGGER_4

#define FIFO_RCV_TRIGGER_4   0x40

Definition at line 153 of file sh4_scifreg.h.

◆ FIFO_RCV_TRIGGER_8

#define FIFO_RCV_TRIGGER_8   0x80

Definition at line 154 of file sh4_scifreg.h.

◆ FIFO_XMT_TRIGGER_1

#define FIFO_XMT_TRIGGER_1   0x30

Definition at line 160 of file sh4_scifreg.h.

◆ FIFO_XMT_TRIGGER_2

#define FIFO_XMT_TRIGGER_2   0x20

Definition at line 159 of file sh4_scifreg.h.

◆ FIFO_XMT_TRIGGER_4

#define FIFO_XMT_TRIGGER_4   0x10

Definition at line 158 of file sh4_scifreg.h.

◆ FIFO_XMT_TRIGGER_8

#define FIFO_XMT_TRIGGER_8   0x00

Definition at line 157 of file sh4_scifreg.h.

◆ SCFCR2_LOOP

#define SCFCR2_LOOP   0x01 /* LOOP back test */

Definition at line 150 of file sh4_scifreg.h.

◆ SCFCR2_MCE

#define SCFCR2_MCE   0x08 /* Modem Control Enable */

Definition at line 147 of file sh4_scifreg.h.

◆ SCFCR2_RFRST

#define SCFCR2_RFRST   0x02 /* Receive Fifo register ReSeT */

Definition at line 149 of file sh4_scifreg.h.

◆ SCFCR2_RTRG0

#define SCFCR2_RTRG0   0x40 /* Receive TRiGger 0 */

Definition at line 144 of file sh4_scifreg.h.

◆ SCFCR2_RTRG1

#define SCFCR2_RTRG1   0x80 /* Receive TRiGger 1 */

Definition at line 143 of file sh4_scifreg.h.

◆ SCFCR2_TFRST

#define SCFCR2_TFRST   0x04 /* Transmit Fifo register ReSeT */

Definition at line 148 of file sh4_scifreg.h.

◆ SCFCR2_TTRG0

#define SCFCR2_TTRG0   0x10 /* Transmit TRiGger 0 */

Definition at line 146 of file sh4_scifreg.h.

◆ SCFCR2_TTRG1

#define SCFCR2_TTRG1   0x20 /* Transmit TRiGger 1 */

Definition at line 145 of file sh4_scifreg.h.

◆ SCFDR2_RECVCNT

#define SCFDR2_RECVCNT   0x00ff /* Rx CouNT */

Definition at line 164 of file sh4_scifreg.h.

◆ SCFDR2_RXF_EPTY

#define SCFDR2_RXF_EPTY   0x0000 /* Rx EMPTY */

Definition at line 166 of file sh4_scifreg.h.

◆ SCFDR2_TXCNT

#define SCFDR2_TXCNT   0xff00 /* Tx CouNT */

Definition at line 163 of file sh4_scifreg.h.

◆ SCFDR2_TXF_FULL

#define SCFDR2_TXF_FULL   0x1000 /* Tx FULL */

Definition at line 165 of file sh4_scifreg.h.

◆ SCIF_BRR

#define SCIF_BRR   0x04 /* bit rate */

Definition at line 68 of file sh4_scifreg.h.

◆ SCIF_FCR

#define SCIF_FCR   0x18 /* fifo control */

Definition at line 73 of file sh4_scifreg.h.

◆ SCIF_FDR

#define SCIF_FDR   0x1c /* fifo data count set */

Definition at line 74 of file sh4_scifreg.h.

◆ SCIF_FRDR

#define SCIF_FRDR   0x14 /* receive fifo data */

Definition at line 72 of file sh4_scifreg.h.

◆ SCIF_FTDR

#define SCIF_FTDR   0x0c /* transmit fifo data */

Definition at line 70 of file sh4_scifreg.h.

◆ SCIF_LSR

#define SCIF_LSR   0x24 /* line status */

Definition at line 77 of file sh4_scifreg.h.

◆ SCIF_SCR

#define SCIF_SCR   0x08 /* serial control */

Definition at line 69 of file sh4_scifreg.h.

◆ SCIF_SMR

#define SCIF_SMR   0x00 /* serial mode */

Definition at line 67 of file sh4_scifreg.h.

◆ SCIF_SPTR

#define SCIF_SPTR   0x20 /* serial port */

Definition at line 76 of file sh4_scifreg.h.

◆ SCIF_SSR

#define SCIF_SSR   0x10 /* serial status */

Definition at line 71 of file sh4_scifreg.h.

◆ SCLSR2_ORER

#define SCLSR2_ORER   0x0001 /* overrun error */

Definition at line 104 of file sh4_scifreg.h.

◆ SCSCR2_CKE0

#define SCSCR2_CKE0   0x01 /* ClocK Enable 0 (not in sh4) */

Definition at line 130 of file sh4_scifreg.h.

◆ SCSCR2_CKE1

#define SCSCR2_CKE1   0x02 /* ClocK Enable 1 */

Definition at line 129 of file sh4_scifreg.h.

◆ SCSCR2_RE

#define SCSCR2_RE   0x10 /* Receive Enable */

Definition at line 128 of file sh4_scifreg.h.

◆ SCSCR2_RIE

#define SCSCR2_RIE   0x40 /* Recieve Interrupt Enable */

Definition at line 126 of file sh4_scifreg.h.

◆ SCSCR2_TE

#define SCSCR2_TE   0x20 /* Transmit Enable */

Definition at line 127 of file sh4_scifreg.h.

◆ SCSCR2_TIE

#define SCSCR2_TIE   0x80 /* Transmit Interrupt Enable */

Definition at line 125 of file sh4_scifreg.h.

◆ SCSMR2_CHR

#define SCSMR2_CHR   0x40 /* character width (set = 7bit) */

Definition at line 109 of file sh4_scifreg.h.

◆ SCSMR2_CKS0

#define SCSMR2_CKS0   0x01 /* ClocK Select 0 */

Definition at line 114 of file sh4_scifreg.h.

◆ SCSMR2_CKS1

#define SCSMR2_CKS1   0x02 /* ClocK Select 1 */

Definition at line 113 of file sh4_scifreg.h.

◆ SCSMR2_ICK0

#define SCSMR2_ICK0   0x08

Definition at line 121 of file sh4_scifreg.h.

◆ SCSMR2_ICK1

#define SCSMR2_ICK1   0x10

Definition at line 120 of file sh4_scifreg.h.

◆ SCSMR2_ICK2

#define SCSMR2_ICK2   0x20

Definition at line 119 of file sh4_scifreg.h.

◆ SCSMR2_ICK3

#define SCSMR2_ICK3   0x40

Definition at line 118 of file sh4_scifreg.h.

◆ SCSMR2_IRMOD

#define SCSMR2_IRMOD   0x80 /* IrDA mode */

Definition at line 117 of file sh4_scifreg.h.

◆ SCSMR2_O

#define SCSMR2_O   0x10 /* parity mode Odd */

Definition at line 111 of file sh4_scifreg.h.

◆ SCSMR2_PE

#define SCSMR2_PE   0x20 /* Parity Enable */

Definition at line 110 of file sh4_scifreg.h.

◆ SCSMR2_PSEL

#define SCSMR2_PSEL   0x04 /* Pulse width SELelect */

Definition at line 122 of file sh4_scifreg.h.

◆ SCSMR2_STOP

#define SCSMR2_STOP   0x08 /* STOP bit (set = 2 stop bits) */

Definition at line 112 of file sh4_scifreg.h.

◆ SCSPTR2_CTSDT

#define SCSPTR2_CTSDT   0x0010

Definition at line 98 of file sh4_scifreg.h.

◆ SCSPTR2_CTSIO

#define SCSPTR2_CTSIO   0x0020

Definition at line 97 of file sh4_scifreg.h.

◆ SCSPTR2_RTSDT

#define SCSPTR2_RTSDT   0x0040

Definition at line 96 of file sh4_scifreg.h.

◆ SCSPTR2_RTSIO

#define SCSPTR2_RTSIO   0x0080

Definition at line 95 of file sh4_scifreg.h.

◆ SCSPTR2_SCKDT

#define SCSPTR2_SCKDT   0x0004

Definition at line 100 of file sh4_scifreg.h.

◆ SCSPTR2_SCKIO

#define SCSPTR2_SCKIO   0x0008

Definition at line 99 of file sh4_scifreg.h.

◆ SCSPTR2_SPB2DT

#define SCSPTR2_SPB2DT   0x0001

Definition at line 102 of file sh4_scifreg.h.

◆ SCSPTR2_SPB2IO

#define SCSPTR2_SPB2IO   0x0002

Definition at line 101 of file sh4_scifreg.h.

◆ SCSSR2_BRK

#define SCSSR2_BRK   0x0010 /* BReaK detection */

Definition at line 136 of file sh4_scifreg.h.

◆ SCSSR2_DR

#define SCSSR2_DR   0x0001 /* Data Ready */

Definition at line 140 of file sh4_scifreg.h.

◆ SCSSR2_ER

#define SCSSR2_ER   0x0080 /* ERror */

Definition at line 133 of file sh4_scifreg.h.

◆ SCSSR2_FER

#define SCSSR2_FER   0x0008 /* Framing ERror */

Definition at line 137 of file sh4_scifreg.h.

◆ SCSSR2_PER

#define SCSSR2_PER   0x0004 /* Parity ERror */

Definition at line 138 of file sh4_scifreg.h.

◆ SCSSR2_RDF

#define SCSSR2_RDF   0x0002 /* Recieve fifo Data Full */

Definition at line 139 of file sh4_scifreg.h.

◆ SCSSR2_TDFE

#define SCSSR2_TDFE   0x0020 /* Transmit Data Fifo Empty */

Definition at line 135 of file sh4_scifreg.h.

◆ SCSSR2_TEND

#define SCSSR2_TEND   0x0040 /* Transmit END */

Definition at line 134 of file sh4_scifreg.h.

◆ SH3_SCIF0_BASE

#define SH3_SCIF0_BASE   0xa4000150

Definition at line 36 of file sh4_scifreg.h.

◆ SH3_SCIF1_BASE

#define SH3_SCIF1_BASE   0xa4000140

Definition at line 37 of file sh4_scifreg.h.

◆ SH4_SCIF_BASE

#define SH4_SCIF_BASE   0xffe80000

Definition at line 39 of file sh4_scifreg.h.

◆ SHREG_SCBRR2

#define SHREG_SCBRR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_BRR))

Definition at line 80 of file sh4_scifreg.h.

◆ SHREG_SCFCR2

#define SHREG_SCFCR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))

Definition at line 85 of file sh4_scifreg.h.

◆ SHREG_SCFDR2

#define SHREG_SCFDR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))

Definition at line 86 of file sh4_scifreg.h.

◆ SHREG_SCFRDR2

#define SHREG_SCFRDR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FRDR))

Definition at line 84 of file sh4_scifreg.h.

◆ SHREG_SCFSR2

#define SHREG_SCFSR2   SHREG_SCSSR2

Definition at line 93 of file sh4_scifreg.h.

◆ SHREG_SCFTDR2

#define SHREG_SCFTDR2   (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FTDR))

Definition at line 82 of file sh4_scifreg.h.

◆ SHREG_SCLSR2

#define SHREG_SCLSR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))

Definition at line 89 of file sh4_scifreg.h.

◆ SHREG_SCSCR2

#define SHREG_SCSCR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))

Definition at line 81 of file sh4_scifreg.h.

◆ SHREG_SCSFDR2

#define SHREG_SCSFDR2   SHREG_SCFTDR2

Definition at line 92 of file sh4_scifreg.h.

◆ SHREG_SCSMR2

#define SHREG_SCSMR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))

Definition at line 79 of file sh4_scifreg.h.

◆ SHREG_SCSPTR2

#define SHREG_SCSPTR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))

Definition at line 88 of file sh4_scifreg.h.

◆ SHREG_SCSSR2

#define SHREG_SCSSR2   (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))

Definition at line 83 of file sh4_scifreg.h.


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