mb86960reg.h Source File

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mb86960reg.h
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1 /* $NetBSD: mb86960reg.h,v 1.10 2005/12/11 12:21:27 christos Exp $ */
2 
3 #ifndef MB86960REG_H
4 #define MB86960REG_H
5 
6 #define MB8696X_NREGS 32
7 
8 /*
9  * All Rights Reserved, Copyright (C) Fujitsu Limited 1995
10  *
11  * This software may be used, modified, copied, distributed, and sold, in
12  * both source and binary form provided that the above copyright, these
13  * terms and the following disclaimer are retained. The name of the author
14  * and/or the contributor may not be used to endorse or promote products
15  * derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /*
31  * Registers of Fujitsu MB86960A/MB86965A Ethernet controller.
32  * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
33  */
34 
35 /*
36  * Notes on register naming:
37  *
38  * Fujitsu documents for MB86960A/MB86965A use no mnemonic names
39  * for their registers. They defined only three names for 32
40  * registers and appended numbers to distinguish registers of
41  * same name. Surprisingly, the numbers represent I/O address
42  * offsets of the registers from the base addresses, and their
43  * names correspond to the "bank" the registers are allocated.
44  * All this means that, for example, to say "read DLCR8" has no more
45  * than to say "read a register at offset 8 on bank DLCR."
46  *
47  * The following definitions may look silly, but that's what Fujitsu
48  * did, and it is necessary to know these names to read Fujitsu
49  * documents..
50  */
51 
52 /* Data Link Control Registers, on invaliant port addresses. */
53 #define FE_DLCR0 0
54 #define FE_DLCR1 1
55 #define FE_DLCR2 2
56 #define FE_DLCR3 3
57 #define FE_DLCR4 4
58 #define FE_DLCR5 5
59 #define FE_DLCR6 6
60 #define FE_DLCR7 7
61 
62 /* More DLCRs, on register bank #0. */
63 #define FE_DLCR8 8
64 #define FE_DLCR9 9
65 #define FE_DLCR10 10
66 #define FE_DLCR11 11
67 #define FE_DLCR12 12
68 #define FE_DLCR13 13
69 #define FE_DLCR14 14
70 #define FE_DLCR15 15
71 
72 /* Multicast Address Registers. On register bank #1. */
73 #define FE_MAR8 8
74 #define FE_MAR9 9
75 #define FE_MAR10 10
76 #define FE_MAR11 11
77 #define FE_MAR12 12
78 #define FE_MAR13 13
79 #define FE_MAR14 14
80 #define FE_MAR15 15
81 
82 /* Buffer Memory Port Registers. On register bank #2. */
83 #define FE_BMPR8 8
84 #define FE_BMPR9 9
85 #define FE_BMPR10 10
86 #define FE_BMPR11 11
87 #define FE_BMPR12 12
88 #define FE_BMPR13 13
89 #define FE_BMPR14 14
90 #define FE_BMPR15 15
91 
92 /* More BMPRs, only on MB86965A, accessible only when JLI mode. */
93 #define FE_BMPR16 16
94 #define FE_BMPR17 17
95 #define FE_BMPR18 18
96 #define FE_BMPR19 19
97 
98 #define FE_RESET 31
99 
100 /*
101  * Definitions of registers.
102  * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't
103  * know the official names for the flags and fields. The following
104  * names are assigned by me (the author of this file), since I cannot
105  * memorize hexadecimal constants for all of these functions.
106  * Comments? FIXME.
107  */
108 
109 /* DLCR0 -- transmitter status */
110 #define FE_D0_BUSERR 0x01 /* Bus write error */
111 #define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */
112 #define FE_D0_COLLID 0x04 /* Collision on last transmission */
113 #define FE_D0_JABBER 0x08 /* Jabber */
114 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
115 #define FE_D0_PKTRCD 0x20 /* No collision on last transmission */
116 #define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */
117 #define FE_D0_TXDONE 0x80 /* Transmission complete */
118 
119 /* DLCR1 -- receiver status */
120 #define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */
121 #define FE_D1_CRCERR 0x02 /* CRC error on last packet */
122 #define FE_D1_ALGERR 0x04 /* Alignment error on last packet */
123 #define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */
124 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
125 #define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */
126 #define FE_D1_BUSERR 0x40 /* Bus read error */
127 #define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */
128 
129 #define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO"
130 
131 /* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */
132 #define FE_D2_BUSERR FE_D0_BUSERR
133 #define FE_D2_COLL16 FE_D0_COLL16
134 #define FE_D2_COLLID FE_D0_COLLID
135 #define FE_D2_JABBER FE_D0_JABBER
136 #define FE_D2_TXDONE FE_D0_TXDONE
137 
138 #define FE_D2_RESERVED 0x70
139 
140 /* DLCR3 -- receiver interrupt control; same layout as DLCR1 */
141 #define FE_D3_OVRFLO FE_D1_OVRFLO
142 #define FE_D3_CRCERR FE_D1_CRCERR
143 #define FE_D3_ALGERR FE_D1_ALGERR
144 #define FE_D3_SRTPKT FE_D1_SRTPKT
145 #define FE_D3_RMTRST FE_D1_RMTRST
146 #define FE_D3_DMAEOP FE_D1_DMAEOP
147 #define FE_D3_BUSERR FE_D1_BUSERR
148 #define FE_D3_PKTRDY FE_D1_PKTRDY
149 
150 /* DLCR4 -- transmitter operation mode */
151 #define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */
152 #define FE_D4_LBC 0x02 /* Loop back test control */
153 #define FE_D4_CNTRL 0x04 /* - ??? */
154 #define FE_D4_TEST1 0x08 /* Test output #1 */
155 #define FE_D4_COL 0xF0 /* Collision counter */
156 
157 #define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */
158 #define FE_D4_LBC_DISABLE 0x02 /* Normal operation */
159 
160 #define FE_D4_COL_SHIFT 4
161 
162 /* DLCR5 -- receiver operation mode */
163 #define FE_D5_AFM0 0x01 /* Receive packets for other stations */
164 #define FE_D5_AFM1 0x02 /* Receive packets for this station */
165 #define FE_D5_RMTRST 0x04 /* Enable remote reset operation */
166 #define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */
167 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
168 #define FE_D5_BADPKT 0x20 /* Accept packets with error */
169 #define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */
170 #define FE_D5_TEST2 0x80 /* Test output #2 */
171 
172 /* DLCR6 -- hardware configuration #0 */
173 #define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */
174 #define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */
175 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
176 #define FE_D6_SBW 0x20 /* System bus width */
177 #define FE_D6_SRAM 0x40 /* Buffer SRAM access time */
178 #define FE_D6_DLC 0x80 /* Disable DLC (receiver/transmitter) */
179 
180 #define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */
181 #define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */
182 #define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */
183 #define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */
184 
185 #define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */
186 #define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */
187 #define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */
188 #define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */
189 
190 #define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */
191 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
192 
193 #define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */
194 #define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */
195 
196 #define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */
197 #define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */
198 
199 #define FE_D6_DLC_ENABLE 0x00 /* Normal operation */
200 #define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */
201 
202 /* DLC7 -- hardware configuration #1 */
203 #define FE_D7_BYTSWP 0x01 /* Host byte order control */
204 #define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */
205 #define FE_D7_RBS 0x0C /* Register bank select */
206 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
207 #define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
208 #define FE_D7_ED 0xC0 /* Encoder/Decoder config (for MB86960) */
209 #define FE_D7_IDENT 0xC0 /* Chip identification */
210 
211 #define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
212 #define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */
213 
214 #define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */
215 #define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */
216 #define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */
217 
218 #define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
219 #define FE_D7_POWER_UP 0x20 /* Normal operation */
220 
221 #define FE_D7_ED_NORMAL 0x00 /* Normal NICE */
222 #define FE_D7_ED_MON 0x40 /* NICE + Monitor */
223 #define FE_D7_ED_BYPASS 0x80 /* Encoder/Decorder Bypass */
224 #define FE_D7_ED_TEST 0xC0 /* Encoder/Decorder Test */
225 
226 #define FE_D7_IDENT_86960 0x00 /* MB86960 (NICE) */
227 #define FE_D7_IDENT_86964 0x40 /* MB86964 */
228 #define FE_D7_IDENT_86967 0x80 /* MB86967 */
229 #define FE_D7_IDENT_86965 0xC0 /* MB86965 (EtherCoupler) */
230 
231 /* DLCR8 thru DLCR13 are for Ethernet station address. */
232 
233 /* DLCR14 and DLCR15 are for TDR (Time Domain Reflectometry). */
234 
235 /* MAR8 thru MAR15 are for Multicast address filter. */
236 
237 /* BMPR8 and BMPR9 are for packet data. */
238 
239 /* BMPR10 -- transmitter start trigger */
240 #define FE_B10_START 0x80 /* Start transmitter */
241 #define FE_B10_COUNT 0x7F /* Packet count */
242 
243 /* BMPR11 -- 16 collisions control */
244 #define FE_B11_CTRL 0x01 /* Skip or resend errored packets */
245 #define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */
246 #define FE_B11_MODE2 0x04 /* Automatic restart enable */
247 
248 #define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */
249 #define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */
250 
251 /* BMPR12 -- DMA enable */
252 #define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */
253 #define FE_B12_RXDMA 0x02 /* Enable receiver DMA */
254 
255 /* BMPR13 -- DMA control */
256 #define FE_B13_BSTCTL 0x03 /* DMA burst mode control */
257 #define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */
258 #define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */
259 #define FE_B13_LNKTST 0x20 /* Link test enable */
260 #define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */
261 #define FE_B13_IOUNLK 0x80 /* Change I/O base address */
262 
263 #define FE_B13_BSTCTL_1 0x00
264 #define FE_B13_BSTCTL_4 0x01
265 #define FE_B13_BSTCTL_8 0x02
266 #define FE_B13_BSTCLT_12 0x03
267 
268 #define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */
269 #define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */
270 
271 #define FE_B13_PORT_AUTO 0x00 /* Auto detected */
272 #define FE_B13_PORT_TP 0x08 /* Force TP */
273 #define FE_B13_PORT_AUI 0x18 /* Force AUI */
274 
275 /* BMPR14 -- More receiver control and more transmission interrupts */
276 #define FE_B14_FILTER 0x01 /* Filter out self-originated packets */
277 #define FE_B14_SQE 0x02 /* SQE interrupt enable */
278 #define FE_B14_SKIP 0x04 /* Skip a received packet */
279 #define FE_B14_RJAB 0x20 /* RJAB interrupt enable */
280 #define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */
281 #define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */
282 
283 /* BMPR15 -- More transmitter status; basically same layout as BMPR14 */
284 #define FE_B15_SQE FE_B14_SQE
285 #define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */
286 #define FE_B15_RMTPRT 0x10 /* ??? */
287 #define FE_B15_RAJB FE_B14_RJAB
288 #define FE_B15_LLD FE_B14_LLD
289 #define FE_B15_RLD FE_B14_RLD
290 
291 /* BMPR16 -- EEPROM control */
292 #define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */
293 #define FE_B16_SELECT 0x20 /* EEPROM chip select */
294 #define FE_B16_CLOCK 0x40 /* EEPROM shift clock */
295 #define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */
296 
297 /* BMPR17 -- EEPROM data */
298 #define FE_B17_DATA 0x80 /* EEPROM data bit */
299 
300 /* BMPR18 I/O Base Address (Only JLI mode) */
301 
302 /* BMPR19 -- Jumperless Setting (Only JLI mode) */
303 #define FE_B19_IRQ 0xC0
304 #define FE_B19_IRQ_SHIFT 6
305 
306 #define FE_B19_ROM 0x38
307 #define FE_B19_ROM_SHIFT 3
308 
309 #define FE_B19_ADDR 0x07
310 #define FE_B19_ADDR_SHIFT 0
311 
312 /*
313  * EEPROM specification (of JLI mode).
314  */
315 
316 /* Number of bytes in an EEPROM accessible through 86965. */
317 #define FE_EEPROM_SIZE 32
318 
319 /* Offset for JLI config; automatically copied into BMPR19 at startup. */
320 #define FE_EEPROM_CONF 0x00
321 
322 /* Delay for 93c06 EEPROM access */
323 #define FE_EEPROM_DELAY() DELAY(4)
324 
325 /*
326  * EEPROM allocation of AT1700/RE2000.
327  */
328 #define FE_ATI_EEP_ADDR 0x08 /* Station address (0x08-0x0d) */
329 #define FE_ATI_EEP_MEDIA 0x18 /* Media type */
330 #define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic */
331 #define FE_ATI_EEP_MODEL 0x1e /* Hardware type */
332 #define FE_ATI_MODEL_AT1700T 0x00
333 #define FE_ATI_MODEL_AT1700BT 0x01
334 #define FE_ATI_MODEL_AT1700FT 0x02
335 #define FE_ATI_MODEL_AT1700AT 0x03
336 #define FE_ATI_EEP_REVISION 0x1f /* Hardware revision */
337 
338 /*
339  * Some 86960 specific constants.
340  */
341 
342 /* Length (in bytes) of a Multicast Address Filter. */
343 #define FE_FILTER_LEN 8
344 
345 /* How many packets we can put in the transmission buffer on NIC memory. */
346 #define FE_QUEUEING_MAX 127
347 
348 /* Size (in bytes) of a "packet length" word in transmission buffer. */
349 #define FE_TXLEN_SIZE 2
350 
351 /* receive packet status in the receive packet header. */
352 #define FE_RXSTAT_GOODPKT 0x20
353 #define FE_RXSTAT_RMT0900 0x10
354 #define FE_RXSTAT_SHORTPKT 0x08
355 #define FE_RXSTAT_ALIGNERR 0x04
356 #define FE_RXSTAT_CRCERR 0x02
357 
358 /*
359  * FUJITSU MBH10302 specific Registers.
360  */
361 
362 #define FE_MBH0 0x10 /* Master interrupt register */
363 #define FE_MBH_ENADDR 0x1A /* Mac address */
364 #define FE_MBH0_MASK 0x0D
365 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts */
366 
367 #endif /* MB86960REG_H */

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