comreg.h File Reference

Back to the index.

Macros
comreg.h File Reference
#include "ns16550reg.h"

Go to the source code of this file.

Macros

#define COM_FREQ   1843200 /* 16-bit baud rate divisor */
 
#define COM_TOLERANCE   30 /* baud rate tolerance, in 0.1% units */
 
#define IER_ERXRDY   0x1 /* Enable receiver interrupt */
 
#define IER_ETXRDY   0x2 /* Enable transmitter empty interrupt */
 
#define IER_ERLS   0x4 /* Enable line status interrupt */
 
#define IER_EMSC   0x8 /* Enable modem status interrupt */
 
#define IER_ERTS   0x40 /* Enable RTS interrupt */
 
#define IER_ECTS   0x80 /* Enable CTS interrupt */
 
#define IIR_IMASK   0xf
 
#define IIR_RXTOUT   0xc
 
#define IIR_RLS   0x6 /* Line status change */
 
#define IIR_RXRDY   0x4 /* Receiver ready */
 
#define IIR_TXRDY   0x2 /* Transmitter ready */
 
#define IIR_MLSC   0x0 /* Modem status */
 
#define IIR_NOPEND   0x1 /* No pending interrupts */
 
#define IIR_FIFO_MASK   0xc0 /* set if FIFOs are enabled */
 
#define FIFO_ENABLE   0x01 /* Turn the FIFO on */
 
#define FIFO_RCV_RST   0x02 /* Reset RX FIFO */
 
#define FIFO_XMT_RST   0x04 /* Reset TX FIFO */
 
#define FIFO_DMA_MODE   0x08
 
#define FIFO_TRIGGER_1   0x00 /* Trigger RXRDY intr on 1 character */
 
#define FIFO_TRIGGER_4   0x40 /* ibid 4 */
 
#define FIFO_TRIGGER_8   0x80 /* ibid 8 */
 
#define FIFO_TRIGGER_14   0xc0 /* ibid 14 */
 
#define EFR_AUTOCTS   0x80 /* Automatic CTS flow control */
 
#define EFR_AUTORTS   0x40 /* Automatic RTS flow control */
 
#define EFR_SPECIAL   0x20 /* Special char detect */
 
#define EFR_EFCR   0x10 /* Enhanced function control bit */
 
#define EFR_TXFLOWBOTH   0x0c /* Automatic transmit XON/XOFF 1 and 2 */
 
#define EFR_TXFLOW1   0x08 /* Automatic transmit XON/XOFF 1 */
 
#define EFR_TXFLOW2   0x04 /* Automatic transmit XON/XOFF 2 */
 
#define EFR_TXFLOWNONE   0x00 /* No automatic XON/XOFF transmit */
 
#define EFR_RXFLOWBOTH   0x03 /* Automatic receive XON/XOFF 1 and 2 */
 
#define EFR_RXFLOW1   0x02 /* Automatic receive XON/XOFF 1 */
 
#define EFR_RXFLOW2   0x01 /* Automatic receive XON/XOFF 2 */
 
#define EFR_RXFLOWNONE   0x00 /* No automatic XON/XOFF receive */
 
#define LCR_EERS   0xBF /* Enable access to Enhanced Register Set */
 
#define LCR_DLAB   0x80 /* Divisor latch access enable */
 
#define LCR_SBREAK   0x40 /* Break Control */
 
#define LCR_PZERO   0x38 /* Space parity */
 
#define LCR_PONE   0x28 /* Mark parity */
 
#define LCR_PEVEN   0x18 /* Even parity */
 
#define LCR_PODD   0x08 /* Odd parity */
 
#define LCR_PNONE   0x00 /* No parity */
 
#define LCR_PENAB   0x08 /* XXX - low order bit of all parity */
 
#define LCR_STOPB   0x04 /* 2 stop bits per serial word */
 
#define LCR_8BITS   0x03 /* 8 bits per serial word */
 
#define LCR_7BITS   0x02 /* 7 bits */
 
#define LCR_6BITS   0x01 /* 6 bits */
 
#define LCR_5BITS   0x00 /* 5 bits */
 
#define MCR_LOOPBACK   0x10 /* Loop test: echos from TX to RX */
 
#define MCR_IENABLE   0x08 /* Out2: enables UART interrupts */
 
#define MCR_DRS   0x04 /* Out1: resets some internal modems */
 
#define MCR_RTS   0x02 /* Request To Send */
 
#define MCR_DTR   0x01 /* Data Terminal Ready */
 
#define LSR_RCV_FIFO   0x80
 
#define LSR_TSRE   0x40 /* Transmitter empty: byte sent */
 
#define LSR_TXRDY   0x20 /* Transmitter buffer empty */
 
#define LSR_BI   0x10 /* Break detected */
 
#define LSR_FE   0x08 /* Framing error: bad stop bit */
 
#define LSR_PE   0x04 /* Parity error */
 
#define LSR_OE   0x02 /* Overrun, lost incoming byte */
 
#define LSR_RXRDY   0x01 /* Byte ready in Receive Buffer */
 
#define LSR_RCV_MASK   0x1f /* Mask for incoming data or error */
 
#define MSR_DCD   0x80 /* Current Data Carrier Detect */
 
#define MSR_RI   0x40 /* Current Ring Indicator */
 
#define MSR_DSR   0x20 /* Current Data Set Ready */
 
#define MSR_CTS   0x10 /* Current Clear to Send */
 
#define MSR_DDCD   0x08 /* DCD has changed state */
 
#define MSR_TERI   0x04 /* RI has toggled low to high */
 
#define MSR_DDSR   0x02 /* DSR has changed state */
 
#define MSR_DCTS   0x01 /* CTS has changed state */
 
#define COM_NPORTS   8
 

Macro Definition Documentation

◆ COM_FREQ

#define COM_FREQ   1843200 /* 16-bit baud rate divisor */

Definition at line 44 of file comreg.h.

◆ COM_NPORTS

#define COM_NPORTS   8

Definition at line 135 of file comreg.h.

◆ COM_TOLERANCE

#define COM_TOLERANCE   30 /* baud rate tolerance, in 0.1% units */

Definition at line 45 of file comreg.h.

◆ EFR_AUTOCTS

#define EFR_AUTOCTS   0x80 /* Automatic CTS flow control */

Definition at line 76 of file comreg.h.

◆ EFR_AUTORTS

#define EFR_AUTORTS   0x40 /* Automatic RTS flow control */

Definition at line 77 of file comreg.h.

◆ EFR_EFCR

#define EFR_EFCR   0x10 /* Enhanced function control bit */

Definition at line 79 of file comreg.h.

◆ EFR_RXFLOW1

#define EFR_RXFLOW1   0x02 /* Automatic receive XON/XOFF 1 */

Definition at line 85 of file comreg.h.

◆ EFR_RXFLOW2

#define EFR_RXFLOW2   0x01 /* Automatic receive XON/XOFF 2 */

Definition at line 86 of file comreg.h.

◆ EFR_RXFLOWBOTH

#define EFR_RXFLOWBOTH   0x03 /* Automatic receive XON/XOFF 1 and 2 */

Definition at line 84 of file comreg.h.

◆ EFR_RXFLOWNONE

#define EFR_RXFLOWNONE   0x00 /* No automatic XON/XOFF receive */

Definition at line 87 of file comreg.h.

◆ EFR_SPECIAL

#define EFR_SPECIAL   0x20 /* Special char detect */

Definition at line 78 of file comreg.h.

◆ EFR_TXFLOW1

#define EFR_TXFLOW1   0x08 /* Automatic transmit XON/XOFF 1 */

Definition at line 81 of file comreg.h.

◆ EFR_TXFLOW2

#define EFR_TXFLOW2   0x04 /* Automatic transmit XON/XOFF 2 */

Definition at line 82 of file comreg.h.

◆ EFR_TXFLOWBOTH

#define EFR_TXFLOWBOTH   0x0c /* Automatic transmit XON/XOFF 1 and 2 */

Definition at line 80 of file comreg.h.

◆ EFR_TXFLOWNONE

#define EFR_TXFLOWNONE   0x00 /* No automatic XON/XOFF transmit */

Definition at line 83 of file comreg.h.

◆ FIFO_DMA_MODE

#define FIFO_DMA_MODE   0x08

Definition at line 69 of file comreg.h.

◆ FIFO_ENABLE

#define FIFO_ENABLE   0x01 /* Turn the FIFO on */

Definition at line 66 of file comreg.h.

◆ FIFO_RCV_RST

#define FIFO_RCV_RST   0x02 /* Reset RX FIFO */

Definition at line 67 of file comreg.h.

◆ FIFO_TRIGGER_1

#define FIFO_TRIGGER_1   0x00 /* Trigger RXRDY intr on 1 character */

Definition at line 70 of file comreg.h.

◆ FIFO_TRIGGER_14

#define FIFO_TRIGGER_14   0xc0 /* ibid 14 */

Definition at line 73 of file comreg.h.

◆ FIFO_TRIGGER_4

#define FIFO_TRIGGER_4   0x40 /* ibid 4 */

Definition at line 71 of file comreg.h.

◆ FIFO_TRIGGER_8

#define FIFO_TRIGGER_8   0x80 /* ibid 8 */

Definition at line 72 of file comreg.h.

◆ FIFO_XMT_RST

#define FIFO_XMT_RST   0x04 /* Reset TX FIFO */

Definition at line 68 of file comreg.h.

◆ IER_ECTS

#define IER_ECTS   0x80 /* Enable CTS interrupt */

Definition at line 53 of file comreg.h.

◆ IER_EMSC

#define IER_EMSC   0x8 /* Enable modem status interrupt */

Definition at line 51 of file comreg.h.

◆ IER_ERLS

#define IER_ERLS   0x4 /* Enable line status interrupt */

Definition at line 50 of file comreg.h.

◆ IER_ERTS

#define IER_ERTS   0x40 /* Enable RTS interrupt */

Definition at line 52 of file comreg.h.

◆ IER_ERXRDY

#define IER_ERXRDY   0x1 /* Enable receiver interrupt */

Definition at line 48 of file comreg.h.

◆ IER_ETXRDY

#define IER_ETXRDY   0x2 /* Enable transmitter empty interrupt */

Definition at line 49 of file comreg.h.

◆ IIR_FIFO_MASK

#define IIR_FIFO_MASK   0xc0 /* set if FIFOs are enabled */

Definition at line 63 of file comreg.h.

◆ IIR_IMASK

#define IIR_IMASK   0xf

Definition at line 56 of file comreg.h.

◆ IIR_MLSC

#define IIR_MLSC   0x0 /* Modem status */

Definition at line 61 of file comreg.h.

◆ IIR_NOPEND

#define IIR_NOPEND   0x1 /* No pending interrupts */

Definition at line 62 of file comreg.h.

◆ IIR_RLS

#define IIR_RLS   0x6 /* Line status change */

Definition at line 58 of file comreg.h.

◆ IIR_RXRDY

#define IIR_RXRDY   0x4 /* Receiver ready */

Definition at line 59 of file comreg.h.

◆ IIR_RXTOUT

#define IIR_RXTOUT   0xc

Definition at line 57 of file comreg.h.

◆ IIR_TXRDY

#define IIR_TXRDY   0x2 /* Transmitter ready */

Definition at line 60 of file comreg.h.

◆ LCR_5BITS

#define LCR_5BITS   0x00 /* 5 bits */

Definition at line 103 of file comreg.h.

◆ LCR_6BITS

#define LCR_6BITS   0x01 /* 6 bits */

Definition at line 102 of file comreg.h.

◆ LCR_7BITS

#define LCR_7BITS   0x02 /* 7 bits */

Definition at line 101 of file comreg.h.

◆ LCR_8BITS

#define LCR_8BITS   0x03 /* 8 bits per serial word */

Definition at line 100 of file comreg.h.

◆ LCR_DLAB

#define LCR_DLAB   0x80 /* Divisor latch access enable */

Definition at line 91 of file comreg.h.

◆ LCR_EERS

#define LCR_EERS   0xBF /* Enable access to Enhanced Register Set */

Definition at line 90 of file comreg.h.

◆ LCR_PENAB

#define LCR_PENAB   0x08 /* XXX - low order bit of all parity */

Definition at line 98 of file comreg.h.

◆ LCR_PEVEN

#define LCR_PEVEN   0x18 /* Even parity */

Definition at line 95 of file comreg.h.

◆ LCR_PNONE

#define LCR_PNONE   0x00 /* No parity */

Definition at line 97 of file comreg.h.

◆ LCR_PODD

#define LCR_PODD   0x08 /* Odd parity */

Definition at line 96 of file comreg.h.

◆ LCR_PONE

#define LCR_PONE   0x28 /* Mark parity */

Definition at line 94 of file comreg.h.

◆ LCR_PZERO

#define LCR_PZERO   0x38 /* Space parity */

Definition at line 93 of file comreg.h.

◆ LCR_SBREAK

#define LCR_SBREAK   0x40 /* Break Control */

Definition at line 92 of file comreg.h.

◆ LCR_STOPB

#define LCR_STOPB   0x04 /* 2 stop bits per serial word */

Definition at line 99 of file comreg.h.

◆ LSR_BI

#define LSR_BI   0x10 /* Break detected */

Definition at line 116 of file comreg.h.

◆ LSR_FE

#define LSR_FE   0x08 /* Framing error: bad stop bit */

Definition at line 117 of file comreg.h.

◆ LSR_OE

#define LSR_OE   0x02 /* Overrun, lost incoming byte */

Definition at line 119 of file comreg.h.

◆ LSR_PE

#define LSR_PE   0x04 /* Parity error */

Definition at line 118 of file comreg.h.

◆ LSR_RCV_FIFO

#define LSR_RCV_FIFO   0x80

Definition at line 113 of file comreg.h.

◆ LSR_RCV_MASK

#define LSR_RCV_MASK   0x1f /* Mask for incoming data or error */

Definition at line 121 of file comreg.h.

◆ LSR_RXRDY

#define LSR_RXRDY   0x01 /* Byte ready in Receive Buffer */

Definition at line 120 of file comreg.h.

◆ LSR_TSRE

#define LSR_TSRE   0x40 /* Transmitter empty: byte sent */

Definition at line 114 of file comreg.h.

◆ LSR_TXRDY

#define LSR_TXRDY   0x20 /* Transmitter buffer empty */

Definition at line 115 of file comreg.h.

◆ MCR_DRS

#define MCR_DRS   0x04 /* Out1: resets some internal modems */

Definition at line 108 of file comreg.h.

◆ MCR_DTR

#define MCR_DTR   0x01 /* Data Terminal Ready */

Definition at line 110 of file comreg.h.

◆ MCR_IENABLE

#define MCR_IENABLE   0x08 /* Out2: enables UART interrupts */

Definition at line 107 of file comreg.h.

◆ MCR_LOOPBACK

#define MCR_LOOPBACK   0x10 /* Loop test: echos from TX to RX */

Definition at line 106 of file comreg.h.

◆ MCR_RTS

#define MCR_RTS   0x02 /* Request To Send */

Definition at line 109 of file comreg.h.

◆ MSR_CTS

#define MSR_CTS   0x10 /* Current Clear to Send */

Definition at line 128 of file comreg.h.

◆ MSR_DCD

#define MSR_DCD   0x80 /* Current Data Carrier Detect */

Definition at line 125 of file comreg.h.

◆ MSR_DCTS

#define MSR_DCTS   0x01 /* CTS has changed state */

Definition at line 132 of file comreg.h.

◆ MSR_DDCD

#define MSR_DDCD   0x08 /* DCD has changed state */

Definition at line 129 of file comreg.h.

◆ MSR_DDSR

#define MSR_DDSR   0x02 /* DSR has changed state */

Definition at line 131 of file comreg.h.

◆ MSR_DSR

#define MSR_DSR   0x20 /* Current Data Set Ready */

Definition at line 127 of file comreg.h.

◆ MSR_RI

#define MSR_RI   0x40 /* Current Ring Indicator */

Definition at line 126 of file comreg.h.

◆ MSR_TERI

#define MSR_TERI   0x04 /* RI has toggled low to high */

Definition at line 130 of file comreg.h.


Generated on Tue Mar 24 2020 14:04:48 for GXemul by doxygen 1.8.17