cpu_sh.h Source File
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61 #define SH_CPU_TYPE_DEFS { \
62 { "SH7708R", 32, 3, 0, 0, }, \
63 { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
64 { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
65 { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
67 { NULL, 0, 0, 0, 0 } }
70 #define SH_N_IC_ARGS 2
71 #define SH_INSTR_ALIGNMENT_SHIFT 1
72 #define SH_IC_ENTRIES_SHIFT 11
73 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
74 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
75 & (SH_IC_ENTRIES_PER_PAGE-1))
76 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
77 + SH_INSTR_ALIGNMENT_SHIFT))
81 #define SH_MAX_VPH_TLB_ENTRIES 128
85 #define SH_N_GPRS_BANKED 8
88 #define SH_N_ITLB_ENTRIES 4
89 #define SH_N_UTLB_ENTRIES 64
93 #define SH_INVALID_INSTR 0x00fb
185 #define SH_SR_T 0x00000001
186 #define SH_SR_S 0x00000002
187 #define SH_SR_IMASK 0x000000f0
188 #define SH_SR_IMASK_SHIFT 4
189 #define SH_SR_Q 0x00000100
190 #define SH_SR_M 0x00000200
191 #define SH_SR_FD 0x00008000
192 #define SH_SR_BL 0x10000000
193 #define SH_SR_RB 0x20000000
194 #define SH_SR_MD 0x40000000
197 #define SH_FPSCR_RM_MASK 0x00000003
198 #define SH_FPSCR_RM_NEAREST 0x0
199 #define SH_FPSCR_RM_ZERO 0x1
200 #define SH_FPSCR_INEXACT 0x00000004
201 #define SH_FPSCR_UNDERFLOW 0x00000008
202 #define SH_FPSCR_OVERFLOW 0x00000010
203 #define SH_FPSCR_DIV_BY_ZERO 0x00000020
204 #define SH_FPSCR_INVALID 0x00000040
205 #define SH_FPSCR_EN_INEXACT 0x00000080
206 #define SH_FPSCR_EN_UNDERFLOW 0x00000100
207 #define SH_FPSCR_EN_OVERFLOW 0x00000200
208 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400
209 #define SH_FPSCR_EN_INVALID 0x00000800
210 #define SH_FPSCR_CAUSE_INEXACT 0x00001000
211 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000
212 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000
213 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000
214 #define SH_FPSCR_CAUSE_INVALID 0x00010000
215 #define SH_FPSCR_CAUSE_ERROR 0x00020000
216 #define SH_FPSCR_DN_ZERO 0x00040000
217 #define SH_FPSCR_PR 0x00080000
218 #define SH_FPSCR_SZ 0x00100000
219 #define SH_FPSCR_FR 0x00200000
223 #define SH_INT_ASSERTED 0x10
224 #define SH_INT_PRIO_MASK 0x0f
232 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
237 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
246 uint64_t *return_addr,
int flags);
#define VPH32(arch, ARCH)
uint32_t dmac_chcr[N_SH4_DMA_CHANNELS]
#define SH_N_UTLB_ENTRIES
void sh_cpu_interrupt_deassert(struct interrupt *interrupt)
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
uint32_t utlb_hi[SH_N_UTLB_ENTRIES]
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
#define N_SH4_DMA_CHANNELS
uint32_t r_bank[SH_N_GPRS_BANKED]
void sh_update_interrupt_priorities(struct cpu *cpu)
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
int sh_cpu_family_init(struct cpu_family *)
uint32_t dmac_tcr[N_SH4_DMA_CHANNELS]
uint32_t dmac_dar[N_SH4_DMA_CHANNELS]
#define DYNTRANS_ITC(arch)
void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
void sh_init_64bit_dummy_tables(struct cpu *cpu)
int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
#define SH_N_ITLB_ENTRIES
#define VPH_TLBS(arch, ARCH)
uint32_t itlb_hi[SH_N_ITLB_ENTRIES]
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
struct pci_data * pcic_pcibus
struct sh_cpu_type_def cpu_type
uint32_t dmac_sar[N_SH4_DMA_CHANNELS]
int sh_run_instr(struct cpu *cpu)
uint32_t utlb_lo[SH_N_UTLB_ENTRIES]
uint8_t int_prio_and_pending[0x1000/0x20]
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
uint32_t itlb_lo[SH_N_ITLB_ENTRIES]
void sh_cpu_interrupt_assert(struct interrupt *interrupt)
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
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