38 int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page) \
39 / sizeof(struct m88k_instr_call); \
40 cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) \
41 << M88K_INSTR_ALIGNMENT_SHIFT); \
42 cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT); \
45 #define ABORT_EXECUTION { SYNCH_PC; \
46 fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \
47 cpu->cd.m88k.next_ic = ¬hing_call; \
49 debugger_n_steps_left_before_interaction = 0; }
69 cpu->
cd.
m88k.next_ic = (
struct m88k_instr_call *)
ic->arg[0];
76 cpu->
cd.
m88k.next_ic = (
struct m88k_instr_call *)
ic->arg[0];
91 cpu->
pc = (uint32_t)((
cpu->
pc & 0xfffff000) + (int32_t)
ic->arg[1]);
174 if (!(
reg(
ic->arg[0]) &
ic->arg[1])) {
181 if (!(
reg(
ic->arg[0]) &
ic->arg[1]))
182 cpu->
cd.
m88k.next_ic = (
struct m88k_instr_call *)
ic->arg[2];
186 int cond = !(
reg(
ic->arg[0]) & (uint32_t)
ic->arg[1]);
213 if (
reg(
ic->arg[0]) &
ic->arg[1]) {
220 if (
reg(
ic->arg[0]) &
ic->arg[1])
221 cpu->
cd.
m88k.next_ic = (
struct m88k_instr_call *)
ic->arg[2];
260 uint32_t mask = 0x80000000, s2 =
reg(
ic->arg[2]);
270 reg(
ic->arg[0]) = 32;
277 uint32_t mask = 0x80000000, s2 =
reg(
ic->arg[2]);
287 reg(
ic->arg[0]) = 32;
300 #define M88K_LOADSTORE_STORE 4
301 #define M88K_LOADSTORE_SIGNEDNESS 8
302 #define M88K_LOADSTORE_ENDIANNESS 16
303 #define M88K_LOADSTORE_SCALEDNESS 32
304 #define M88K_LOADSTORE_USR 64
305 #define M88K_LOADSTORE_REGISTEROFFSET 128
411 static void m88k_cmp(
struct cpu *
cpu,
struct m88k_instr_call *
ic, uint32_t y)
413 uint32_t x =
reg(
ic->arg[1]);
424 if ((int32_t)x > (int32_t)y)
451 static void m88k_extu(
struct cpu *
cpu,
struct m88k_instr_call *
ic,
int w,
int o)
453 uint32_t x =
reg(
ic->arg[1]) >> o;
460 static void m88k_ext(
struct cpu *
cpu,
struct m88k_instr_call *
ic,
int w,
int o)
462 int32_t x =
reg(
ic->arg[1]);
470 static void m88k_mak(
struct cpu *
cpu,
struct m88k_instr_call *
ic,
int w,
int o)
472 uint32_t x =
reg(
ic->arg[1]);
477 reg(
ic->arg[0]) = x << o;
481 m88k_extu(
cpu,
ic,
ic->arg[2] >> 5,
ic->arg[2] & 0x1f);
485 m88k_extu(
cpu,
ic, (
reg(
ic->arg[2]) >> 5) & 0x1f,
486 reg(
ic->arg[2]) & 0x1f);
490 m88k_ext(
cpu,
ic,
ic->arg[2] >> 5,
ic->arg[2] & 0x1f);
494 m88k_ext(
cpu,
ic, (
reg(
ic->arg[2]) >> 5) & 0x1f,
495 reg(
ic->arg[2]) & 0x1f);
499 m88k_mak(
cpu,
ic,
ic->arg[2] >> 5,
ic->arg[2] & 0x1f);
503 m88k_mak(
cpu,
ic, (
reg(
ic->arg[2]) >> 5) & 0x1f,
504 reg(
ic->arg[2]) & 0x1f);
506 static void m88k_rot(
struct cpu *
cpu,
struct m88k_instr_call *
ic,
int n)
508 uint32_t x =
reg(
ic->arg[1]);
511 uint32_t mask = (1 << n) - 1;
512 uint32_t bits = x & mask;
514 x |= (bits << (32-n));
525 int w = (
reg(
ic->arg[2]) >> 5) & 0x1f, o =
reg(
ic->arg[2]) & 0x1f;
526 uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
532 int w = (
reg(
ic->arg[2]) >> 5) & 0x1f, o =
reg(
ic->arg[2]) & 0x1f;
533 uint32_t x = w == 0? 0xffffffff : ((uint32_t)1 << w) - 1;
566 | (
reg(
ic->arg[1]) & 0xffff0000); }
568 | (
reg(
ic->arg[1]) & 0xffff); }
572 uint64_t a = (int32_t)
reg(
ic->arg[1]);
573 uint64_t b =
ic->arg[2];
574 uint64_t res = a + b;
575 uint64_t res2 = (int32_t) res;
583 reg(
ic->arg[0]) = res;
604 }
else if (
ic->arg[2] == 0) {
608 reg(
ic->arg[0]) = (uint32_t)
reg(
ic->arg[1]) / (uint32_t)
ic->arg[2];
616 }
else if (
ic->arg[2] == 0) {
620 int32_t res = (int32_t)
reg(
ic->arg[1]) / (int32_t)
ic->arg[2];
621 reg(
ic->arg[0]) = res;
626 uint64_t a = (int32_t)
reg(
ic->arg[1]);
627 uint64_t b =
ic->arg[2];
628 uint64_t res = a - b;
629 uint64_t res2 = (int32_t) res;
637 reg(
ic->arg[0]) = res;
680 uint64_t s1 = (int32_t)
reg(
ic->arg[1]);
681 uint64_t s2 = (int32_t)
reg(
ic->arg[2]);
682 uint64_t d = s1 + s2;
683 uint64_t dx = (int32_t) d;
709 }
else if (
reg(
ic->arg[2]) == 0) {
713 reg(
ic->arg[0]) = (uint32_t)
reg(
ic->arg[1]) / (uint32_t)
reg(
ic->arg[2]);
721 }
else if (
reg(
ic->arg[2]) == 0) {
725 int32_t res = (int32_t)
reg(
ic->arg[1]) / (int32_t)
reg(
ic->arg[2]);
726 reg(
ic->arg[0]) = res;
731 uint64_t a =
reg(
ic->arg[1]), b =
reg(
ic->arg[2]);
740 uint32_t result =
reg(
ic->arg[1]) +
reg(
ic->arg[2]);
743 reg(
ic->arg[0]) = result;
747 uint64_t a =
reg(
ic->arg[1]), b =
reg(
ic->arg[2]);
756 uint32_t result =
reg(
ic->arg[1]) -
reg(
ic->arg[2]);
759 reg(
ic->arg[0]) = result;
840 uint32_t s2 =
reg(
ic->arg[2]);
841 uint32_t s1 =
reg(
ic->arg[1]);
862 uint64_t s2 =
reg(
ic->arg[2]);
863 uint32_t s1 =
reg(
ic->arg[1]);
864 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
878 reg(
ic->arg[0]) = d >> 32;
879 reg(
ic->arg[0] + 4) = d;
886 uint32_t s2 =
reg(
ic->arg[2]);
887 uint64_t s1 =
reg(
ic->arg[1]);
888 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
902 reg(
ic->arg[0]) = d >> 32;
903 reg(
ic->arg[0] + 4) = d;
910 uint64_t s1 =
reg(
ic->arg[1]);
911 uint64_t s2 =
reg(
ic->arg[2]);
912 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
913 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
927 reg(
ic->arg[0]) = d >> 32;
928 reg(
ic->arg[0] + 4) = d;
935 uint32_t s2 =
reg(
ic->arg[2]);
936 uint64_t s1 =
reg(
ic->arg[1]);
937 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
957 uint32_t s2 =
reg(
ic->arg[2]);
958 uint32_t s1 =
reg(
ic->arg[1]);
972 reg(
ic->arg[0]) = d >> 32;
973 reg(
ic->arg[0] + 4) = d;
980 uint64_t s2 =
reg(
ic->arg[2]);
981 uint32_t s1 =
reg(
ic->arg[1]);
982 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
996 reg(
ic->arg[0]) = d >> 32;
997 reg(
ic->arg[0] + 4) = d;
1004 uint32_t s2 =
reg(
ic->arg[2]);
1005 uint64_t s1 =
reg(
ic->arg[1]);
1006 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1020 reg(
ic->arg[0]) = d >> 32;
1021 reg(
ic->arg[0] + 4) = d;
1028 uint64_t s1 =
reg(
ic->arg[1]);
1029 uint64_t s2 =
reg(
ic->arg[2]);
1030 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1031 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1045 reg(
ic->arg[0]) = d >> 32;
1046 reg(
ic->arg[0] + 4) = d;
1053 uint32_t s2 =
reg(
ic->arg[2]);
1054 uint32_t s1 =
reg(
ic->arg[1]);
1067 reg(
ic->arg[0]) = d;
1074 uint32_t s2 =
reg(
ic->arg[2]);
1075 uint32_t s1 =
reg(
ic->arg[1]);
1089 reg(
ic->arg[0]) = d >> 32;
1090 reg(
ic->arg[0] + 4) = d;
1097 uint64_t s2 =
reg(
ic->arg[2]);
1098 uint32_t s1 =
reg(
ic->arg[1]);
1099 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1113 reg(
ic->arg[0]) = d >> 32;
1114 reg(
ic->arg[0] + 4) = d;
1121 uint32_t s2 =
reg(
ic->arg[2]);
1122 uint64_t s1 =
reg(
ic->arg[1]);
1123 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1137 reg(
ic->arg[0]) = d >> 32;
1138 reg(
ic->arg[0] + 4) = d;
1145 uint64_t s1 =
reg(
ic->arg[1]);
1146 uint64_t s2 =
reg(
ic->arg[2]);
1147 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1148 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1162 reg(
ic->arg[0]) = d >> 32;
1163 reg(
ic->arg[0] + 4) = d;
1170 uint32_t s1 =
reg(
ic->arg[1]);
1171 uint32_t s2 =
reg(
ic->arg[2]);
1192 reg(
ic->arg[0]) = d;
1199 uint32_t s1 =
reg(
ic->arg[1]);
1200 uint64_t s2 =
reg(
ic->arg[2]);
1201 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1222 reg(
ic->arg[0]) = d >> 32;
1223 reg(
ic->arg[0] + 4) = d;
1230 uint64_t s1 =
reg(
ic->arg[1]);
1231 uint64_t s2 =
reg(
ic->arg[2]);
1232 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1233 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1254 reg(
ic->arg[0]) = d >> 32;
1255 reg(
ic->arg[0] + 4) = d;
1275 if (isnan(f1->
f) || isnan(f2->
f))
1299 uint32_t s2 =
reg(
ic->arg[2]);
1300 uint64_t s1 =
reg(
ic->arg[1]);
1301 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1312 reg(
ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
1318 uint64_t s1 =
reg(
ic->arg[1]);
1319 uint64_t s2 =
reg(
ic->arg[2]);
1320 s1 = (s1 << 32) +
reg(
ic->arg[1] + 4);
1321 s2 = (s2 << 32) +
reg(
ic->arg[2] + 4);
1332 reg(
ic->arg[0]) = m88k_fcmp_common(&f1, &f2);
1346 int32_t x =
reg(
ic->arg[1]);
1359 int32_t x =
reg(
ic->arg[1]);
1371 reg(
ic->arg[0]) = result >> 32;
1372 reg(
ic->arg[0] + 4) = result;
1396 reg(
ic->arg[0]) = (int32_t) f1.
f;
1401 uint64_t x =
reg(
ic->arg[1]);
1402 x = (x << 32) +
reg(
ic->arg[1] + 4);
1412 reg(
ic->arg[0]) = (int32_t) f1.
f;
1429 tmp =
reg(
ic->arg[1]);
1432 reg(
ic->arg[0]) = tmp2;
1453 fatal(
"rte: NIP: TODO: single-step support\n");
1458 fatal(
"rte: TODO: FIP single-step support\n");
1471 fatal(
"[ TODO: Neither FIP nor NIP has the "
1472 "Valid bit set?! ]\n");
1498 if (
cpu->
pc != nip) {
1499 fatal(
"NIP execution caused exception?! TODO\n");
1505 if ((
cpu->
pc & 0xfffff000) != (nip & 0xfffff000)) {
1506 fatal(
"instruction in delay slot when returning via"
1507 " rte caused an exception?! nip=0x%08x, but pc "
1508 "changed to 0x%08x! TODO\n", nip, (
int)
cpu->
pc);
1525 fatal(
"RTE failed. NIP=0x%08" PRIx32
", FIP=0x%08" PRIx32
"\n",
1539 uint32_t iword =
ic->arg[0],
addr;
1542 int d = (iword >> 21) & 0x1f;
1543 int s1 = (iword >> 16) & 0x1f;
1544 int s2 = iword & 0x1f;
1545 int imm16 = iword & 0xffff;
1546 int scaled = iword & 0x200;
1547 int size = iword & 0x400;
1548 int user = iword & 0x80;
1553 fatal(
"xmem_slow: user: not yet (TODO)\n");
1557 if ((iword & 0xf0000000) == 0) {
1561 size = (iword >> 26) & 1;
1567 addr *=
sizeof(uint32_t);
1580 uint32_t *p = (uint32_t *) tmp;
1596 fatal(
"XMEM exception: TODO: update the transaction"
1606 fatal(
"XMEM exception: TODO: update the transaction"
1614 uint32_t *p = (uint32_t *)
data;
1649 default:
fatal(
"m88k prom_call: unimplemented machine type\n");
1677 if (!(
reg(
ic->arg[1]) &
ic->arg[0]))
1690 if (
reg(
ic->arg[1]) &
ic->arg[0])
1703 uint32_t rY =
reg(
ic[0].arg[1]) +
ic[0].arg[2];
1704 uint32_t index = rY >> 12;
1705 unsigned char *p =
cpu->
cd.
m88k.host_load[index];
1706 uint32_t *p32 = (uint32_t *) p;
1710 if (p == NULL || (rY & 3)) {
1715 v = p32[(rY & 0xfff) >> 2];
1721 reg(
ic[0].arg[0]) = v;
1745 uint32_t rY =
reg(
ic[1].arg[1]) +
ic[1].arg[2];
1746 uint32_t index = rY >> 12;
1747 unsigned char *p =
cpu->
cd.
m88k.host_load[index];
1748 uint32_t *p32 = (uint32_t *) p;
1752 if (p == NULL || (rY & 3)) {
1757 v = p32[(rY & 0xfff) >> 2];
1763 reg(
ic[1].arg[0]) = v;
1833 int low_pc = ((size_t)
ic - (
size_t)
cpu->
cd.
m88k.cur_ic_page)
1834 /
sizeof(
struct m88k_instr_call);
1841 printf(
"[ end_of_page2: HUH? low_pc=%i, cpu->pc = %08"
1842 PRIx32
" ]\n", low_pc, (uint32_t)
cpu->
pc);
1853 fatal(
"end_of_page2: fatal error, we're in a delay slot\n");
1880 if (
ic[0].
f ==
instr(bcnd_samepage_eq0) &&
1881 ic[0].arg[2] == (size_t) &
ic[-1] &&
1883 ic[0].arg[0] ==
ic[-1].arg[0] &&
1889 if (
ic[0].
f ==
instr(bcnd_samepage_eq0) &&
1890 ic[0].arg[2] == (
size_t) &
ic[-2] &&
1893 ic[-1].f ==
instr(ld_u_4_be) &&
1894 ic[0].arg[0] ==
ic[-1].arg[0] &&
1896 ic[-2].f =
instr(idle_with_tb1);
1915 uint32_t
addr, low_pc, iword;
1916 unsigned char *
page;
1917 unsigned char ib[4];
1918 uint32_t op26, op10, op11, d, s1, s2, cr6, imm16;
1921 int in_crosspage_delayslot = 0;
1922 void (*samepage_function)(
struct cpu *,
struct m88k_instr_call *)=NULL;
1925 low_pc = ((size_t)
ic - (
size_t)
cpu->
cd.
m88k.cur_ic_page)
1926 /
sizeof(
struct m88k_instr_call);
1932 in_crosspage_delayslot = 1;
1946 memcpy(ib,
page + (
addr & 0xffc),
sizeof(ib));
1951 fatal(
"to_be_translated(): read failed: TODO\n");
1957 uint32_t *p = (uint32_t *) ib;
1967 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
1969 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
1981 fatal(
"INTERNAL ERROR! M88K_ZERO_REG != 0?\n");
1985 op26 = (iword >> 26) & 0x3f;
1986 op11 = (iword >> 11) & 0x1f;
1987 op10 = (iword >> 10) & 0x3f;
1988 d = (iword >> 21) & 0x1f;
1989 s1 = (iword >> 16) & 0x1f;
1991 imm16 = iword & 0xffff;
1993 cr6 = (iword >> 5) & 0x3f;
1994 d16 = ((int16_t) (iword & 0xffff)) * 4;
1995 d26 = ((int32_t)((iword & 0x03ffffff) << 6)) >> 4;
2020 int store = 0, signedness = 0, opsize = 0;
2027 case 0x02: opsize = 1;
break;
2028 case 0x03: opsize = 0;
break;
2029 case 0x04: opsize = 3;
break;
2030 case 0x05: opsize = 2;
break;
2031 case 0x06: opsize = 1; signedness = 1;
break;
2032 case 0x07: opsize = 0; signedness = 1;
break;
2033 case 0x08: store = 1; opsize = 3;
break;
2034 case 0x09: store = 1; opsize = 2;
break;
2035 case 0x0a: store = 1; opsize = 1;
break;
2036 case 0x0b: store = 1; opsize = 0;
break;
2039 if (opsize == 3 && d == 31) {
2040 fatal(
"m88k load/store of register pair r31/r0"
2041 " is not yet implemented\n");
2051 if (!store && d == 0)
2074 case 0x10:
ic->f =
instr(and_imm);
break;
2075 case 0x11:
ic->f =
instr(and_u_imm); shift = 16;
break;
2076 case 0x12:
ic->f =
instr(mask_imm);
break;
2077 case 0x13:
ic->f =
instr(mask_imm); shift = 16;
break;
2078 case 0x14:
ic->f =
instr(xor_imm);
break;
2079 case 0x15:
ic->f =
instr(xor_imm); shift = 16;
break;
2080 case 0x16:
ic->f =
instr(or_imm);
break;
2081 case 0x17:
ic->f =
instr(or_imm); shift = 16;
break;
2082 case 0x18:
ic->f =
instr(addu_imm);
break;
2083 case 0x19:
ic->f =
instr(subu_imm);
break;
2084 case 0x1a:
ic->f =
instr(divu_imm);
break;
2085 case 0x1b:
ic->f =
instr(mulu_imm);
break;
2086 case 0x1c:
ic->f =
instr(add_imm);
break;
2087 case 0x1d:
ic->f =
instr(sub_imm);
break;
2088 case 0x1e:
ic->f =
instr(div_imm);
break;
2089 case 0x1f:
ic->f =
instr(cmp_imm);
break;
2094 ic->arg[2] = imm16 << shift;
2098 if (
ic->arg[2] == 0)
2103 if (
ic->arg[2] == 0 &&
ic->f ==
instr(addu_imm))
2106 if (d == s1 &&
ic->arg[2] == 1) {
2118 if ((iword & 0x001ff81f) == 0x00004000) {
2123 ic->arg[0] = (size_t)
2125 }
else if ((iword & 0x001ff81f) == 0x00004800) {
2130 ic->arg[0] = (size_t)
2132 }
else if ((iword & 0x03e0f800) == 0x00008000) {
2138 }
else if ((iword & 0x03e0f800) == 0x00008800) {
2144 }
else if ((iword & 0x0000f800) == 0x0000c000) {
2161 fatal(
"TODO: exception for d = 0 in fmul.xxx instruction\n");
2167 switch ((iword >> 5) & 0x3f) {
2168 case 0x00:
ic->f =
instr(fmul_sss);
break;
2169 case 0x01:
ic->f =
instr(fmul_dss);
break;
2170 case 0x05:
ic->f =
instr(fmul_dsd);
break;
2171 case 0x11:
ic->f =
instr(fmul_dds);
break;
2172 case 0x15:
ic->f =
instr(fmul_ddd);
break;
2174 fatal(
"Unimplemented fmul combination 0x%x.\n",
2175 (iword >> 5) & 0x3f);
2183 fatal(
"TODO: exception for d = 0 in flt.xx instruction\n");
2188 if ((iword >> 5) & 1) {
2191 fatal(
"TODO: double precision load into uneven register r%i?\n", d);
2202 fatal(
"TODO: exception for d = 0 in fadd.xxx instruction\n");
2208 switch ((iword >> 5) & 0x3f) {
2209 case 0x00:
ic->f =
instr(fadd_sss);
break;
2210 case 0x05:
ic->f =
instr(fadd_dsd);
break;
2211 case 0x11:
ic->f =
instr(fadd_dds);
break;
2212 case 0x15:
ic->f =
instr(fadd_ddd);
break;
2214 fatal(
"Unimplemented fadd combination 0x%x.\n",
2215 (iword >> 5) & 0x3f);
2223 fatal(
"TODO: exception for d = 0 in fsub.xxx instruction\n");
2229 switch ((iword >> 5) & 0x3f) {
2230 case 0x01:
ic->f =
instr(fsub_dss);
break;
2231 case 0x05:
ic->f =
instr(fsub_dsd);
break;
2232 case 0x10:
ic->f =
instr(fsub_sds);
break;
2233 case 0x11:
ic->f =
instr(fsub_dds);
break;
2234 case 0x15:
ic->f =
instr(fsub_ddd);
break;
2236 fatal(
"Unimplemented fsub combination 0x%x.\n",
2237 (iword >> 5) & 0x3f);
2245 fatal(
"TODO: exception for d = 0 in fcmp.xxx instruction\n");
2251 switch ((iword >> 5) & 0x3f) {
2252 case 0x10:
ic->f =
instr(fcmp_sds);
break;
2253 case 0x14:
ic->f =
instr(fcmp_sdd);
break;
2255 fatal(
"Unimplemented fcmp combination 0x%x.\n",
2256 (iword >> 5) & 0x3f);
2264 fatal(
"TODO: exception for d = 0 in trnc.xx instruction\n");
2269 if ((iword >> 7) & 1) {
2272 fatal(
"TODO: double precision truncation into uneven register r%i?\n", d);
2283 fatal(
"TODO: exception for d = 0 in fdiv.xxx instruction\n");
2289 switch ((iword >> 5) & 0x3f) {
2290 case 0x00:
ic->f =
instr(fdiv_sss);
break;
2291 case 0x05:
ic->f =
instr(fdiv_dsd);
break;
2292 case 0x15:
ic->f =
instr(fdiv_ddd);
break;
2294 fatal(
"Unimplemented fdiv combination 0x%x.\n",
2295 (iword >> 5) & 0x3f);
2311 samepage_function =
instr(br_samepage);
2322 samepage_function =
instr(bsr_samepage);
2329 offset = (
addr & 0xffc) + d26;
2333 ic->arg[0] = (size_t) (
cpu->
cd.
m88k.cur_ic_page +
2335 ic->arg[1] = offset;
2336 ic->arg[2] = (
addr & 0xffc) + 4;
2339 if (offset >= 0 && offset <= 0xffc &&
2340 samepage_function != NULL)
2341 ic->f = samepage_function;
2359 samepage_function =
instr(bb0_samepage);
2366 samepage_function =
instr(bb1_samepage);
2374 ic->arg[1] = (uint32_t) (1 << d);
2376 offset = (
addr & 0xffc) + d16;
2377 ic->arg[2] = offset;
2379 if (offset >= 0 && offset <= 0xffc &&
2380 samepage_function != NULL) {
2381 ic->f = samepage_function;
2382 ic->arg[2] = (size_t) (
cpu->
cd.
m88k.cur_ic_page +
2390 samepage_function =
m88k_bcnd[64 + d + 32 * (op26 & 1)];
2397 offset = (
addr & 0xffc) + d16;
2398 ic->arg[2] = offset;
2400 if (offset >= 0 && offset <= 0xffc &&
2401 samepage_function != NULL) {
2402 ic->f = samepage_function;
2403 ic->arg[2] = (size_t) (
cpu->
cd.
m88k.cur_ic_page +
2407 if ((iword & 0xffe0ffff) == 0xe840ffff ||
2408 (iword & 0xffe0ffff) == 0xe840fffe)
2423 ic->arg[2] = iword & 0x3ff;
2426 case 0x20:
ic->f =
instr(mask_imm);
2428 int w =
ic->arg[2] >> 5;
2429 int o =
ic->arg[2] & 0x1f;
2430 uint32_t x = w == 0? 0xffffffff
2431 : ((uint32_t)1 << w) - 1;
2436 case 0x22:
ic->f =
instr(or_imm);
2438 int w =
ic->arg[2] >> 5;
2439 int o =
ic->arg[2] & 0x1f;
2440 uint32_t x = w == 0? 0xffffffff
2441 : ((uint32_t)1 << w) - 1;
2446 case 0x24:
ic->f =
instr(ext_imm);
break;
2447 case 0x26:
ic->f =
instr(extu_imm);
break;
2448 case 0x28:
ic->f =
instr(mak_imm);
break;
2457 ic->arg[0] = 1 << d;
2459 ic->arg[2] = iword & 0x1ff;
2461 case 0x34:
ic->f =
instr(tb0);
break;
2462 case 0x36:
ic->f =
instr(tb1);
break;
2471 if ((iword & 0xf000) <= 0x3fff ) {
2473 int op = 0, opsize, user = 0, wt = 0;
2474 int signedness = 1, scaled = 0;
2476 switch (iword & 0xf000) {
2477 case 0x2000:
op = 1;
break;
2478 case 0x3000:
op = 2;
break;
2479 default:
if ((iword & 0xf800) >= 0x0800)
2486 opsize = (iword >> 10) & 3;
2489 opsize = 3 - opsize;
2493 switch ((iword >> 10) & 3) {
2494 case 0: opsize = 0;
break;
2495 case 1: opsize = 2;
break;
2496 default:
fatal(
"Weird xmem opsize/type?\n");
2500 if ((iword & 0xf800) == 0x800) {
2502 if ((iword & 0xf00) < 0xc00)
2507 if (opsize >= 2 ||
op == 1)
2520 fatal(
"wt bit not yet implemented! TODO\n");
2528 if (
op == 0 ||
op == 1) {
2542 if (opsize == 3 && d == 31) {
2543 fatal(
"m88k load/store of register "
2544 "pair r31/r0: TODO\n");
2547 }
else if (
op == 2) {
2552 case 1:
ic->f =
instr(lda_reg_2);
break;
2553 case 2:
ic->f =
instr(lda_reg_4);
break;
2554 case 3:
ic->f =
instr(lda_reg_8);
break;
2568 }
else switch ((iword >> 8) & 0xff) {
2596 switch ((iword >> 8) & 0xff) {
2597 case 0x40:
ic->f =
instr(and);
break;
2598 case 0x44:
ic->f =
instr(and_c);
break;
2599 case 0x50:
ic->f =
instr(xor);
break;
2600 case 0x54:
ic->f =
instr(xor_c);
break;
2601 case 0x58:
ic->f =
instr(or);
break;
2602 case 0x5c:
ic->f =
instr(or_c);
break;
2604 case 0x61:
ic->f =
instr(addu_co);
break;
2605 case 0x62:
ic->f =
instr(addu_ci);
break;
2606 case 0x64:
ic->f =
instr(subu);
break;
2607 case 0x65:
ic->f =
instr(subu_co);
break;
2608 case 0x66:
ic->f =
instr(subu_ci);
break;
2609 case 0x68:
ic->f =
instr(divu);
break;
2610 case 0x6c:
ic->f =
instr(mul);
break;
2611 case 0x70:
ic->f =
instr(add);
break;
2612 case 0x78:
ic->f =
instr(div);
break;
2613 case 0x7c:
ic->f =
instr(cmp);
break;
2614 case 0x80:
ic->f =
instr(clr);
break;
2615 case 0x88:
ic->f =
instr(set);
break;
2616 case 0x90:
ic->f =
instr(ext);
break;
2617 case 0x98:
ic->f =
instr(extu);
break;
2618 case 0xa0:
ic->f =
instr(mak);
break;
2619 case 0xa8:
ic->f =
instr(rot);
break;
2638 int opc = (iword >> 8) & 0xff;
2639 if (opc != 0x61 && opc != 0x63 &&
2640 opc != 0x65 && opc != 0x67 &&
2641 opc != 0x71 && opc != 0x73 &&
2642 opc != 0x75 && opc != 0x77 &&
2643 opc != 0x68 && opc != 0x69 &&
2644 opc != 0x6c && opc != 0x6d &&
2645 opc != 0x6e && opc != 0x78 )
2648 ic->arg[0] = (size_t)
2656 switch ((iword >> 8) & 0xff) {
2657 case 0xc0:
ic->f =
instr(jmp);
2661 case 0xc4:
ic->f =
instr(jmp_n);
2665 case 0xc8:
ic->f =
instr(jsr);
break;
2666 case 0xcc:
ic->f =
instr(jsr_n);
break;
2669 ic->arg[1] = (
addr & 0xffc) + 4;
2672 if (((iword >> 8) & 0x04) == 0x04)
2673 ic->arg[1] = (
addr & 0xffc) + 8;
2691 switch ((iword >> 8) & 0xff) {
2692 case 0xe8:
ic->f =
instr(ff1);
break;
2693 case 0xec:
ic->f =
instr(ff0);
break;
2703 switch (iword & 0xff) {
2705 if (iword == 0xf400fc00)
2708 fatal(
"unimplemented rte variant: 0x%08" PRIx32
"\n", iword);
2715 default:
fatal(
"Unimplemented 3d/fc instruction\n");
2727 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
2729 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL