armreg.h File Reference

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armreg.h File Reference
#include "thirdparty/arm_cputypes.h"

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Macros

#define PSR_FLAGS   0xf0000000 /* flags */
 
#define PSR_N_bit   (1 << 31) /* negative */
 
#define PSR_Z_bit   (1 << 30) /* zero */
 
#define PSR_C_bit   (1 << 29) /* carry */
 
#define PSR_V_bit   (1 << 28) /* overflow */
 
#define PSR_Q_bit   (1 << 27) /* saturation */
 
#define PSR_IT1_bit   (1 << 26)
 
#define PSR_IT0_bit   (1 << 25)
 
#define PSR_J_bit   (1 << 24) /* Jazelle mode */
 
#define PSR_GE_bits   (15 << 16) /* SIMD GE bits */
 
#define PSR_IT7_bit   (1 << 15)
 
#define PSR_IT6_bit   (1 << 14)
 
#define PSR_IT5_bit   (1 << 13)
 
#define PSR_IT4_bit   (1 << 12)
 
#define PSR_IT3_bit   (1 << 11)
 
#define PSR_IT2_bit   (1 << 10)
 
#define PSR_E_BIT   (1 << 9) /* Endian state */
 
#define PSR_A_BIT   (1 << 8) /* Async abort disable */
 
#define I32_bit   (1 << 7) /* IRQ disable */
 
#define F32_bit   (1 << 6) /* FIQ disable */
 
#define IF32_bits   (3 << 6) /* IRQ/FIQ disable */
 
#define PSR_T_bit   (1 << 5) /* Thumb state */
 
#define PSR_MODE   0x0000001f /* mode mask */
 
#define PSR_USR32_MODE   0x00000010
 
#define PSR_FIQ32_MODE   0x00000011
 
#define PSR_IRQ32_MODE   0x00000012
 
#define PSR_SVC32_MODE   0x00000013
 
#define PSR_MON32_MODE   0x00000016
 
#define PSR_ABT32_MODE   0x00000017
 
#define PSR_HYP32_MODE   0x0000001a
 
#define PSR_UND32_MODE   0x0000001b
 
#define PSR_SYS32_MODE   0x0000001f
 
#define PSR_32_MODE   0x00000010
 
#define R15_FLAGS   0xf0000000
 
#define R15_FLAG_N   0x80000000
 
#define R15_FLAG_Z   0x40000000
 
#define R15_FLAG_C   0x20000000
 
#define R15_FLAG_V   0x10000000
 
#define ARM_CP15_CPU_ID   0
 
#define ARM_ISA3_SYNCHPRIM_MASK   0x0000f000
 
#define ARM_ISA4_SYNCHPRIM_MASK   0x00f00000
 
#define ARM_ISA3_SYNCHPRIM_LDREX   0x10
 
#define ARM_ISA3_SYNCHPRIM_LDREXPLUS   0x13
 
#define ARM_ISA3_SYNCHPRIM_LDREXD   0x20
 
#define ARM_PFR0_THUMBEE_MASK   0x0000f000
 
#define ARM_PFR1_GTIMER_MASK   0x000f0000
 
#define ARM_PFR1_VIRT_MASK   0x0000f000
 
#define ARM_PFR1_SEC_MASK   0x000000f0
 
#define ARM_MVFR0_ROUNDING_MASK   0xf0000000
 
#define ARM_MVFR0_SHORTVEC_MASK   0x0f000000
 
#define ARM_MVFR0_SQRT_MASK   0x00f00000
 
#define ARM_MVFR0_DIVIDE_MASK   0x000f0000
 
#define ARM_MVFR0_EXCEPT_MASK   0x0000f000
 
#define ARM_MVFR0_DFLOAT_MASK   0x00000f00
 
#define ARM_MVFR0_SFLOAT_MASK   0x000000f0
 
#define ARM_MVFR0_ASIMD_MASK   0x0000000f
 
#define ARM_MVFR1_ASIMD_FMACS_MASK   0xf0000000
 
#define ARM_MVFR1_VFP_HPFP_MASK   0x0f000000
 
#define ARM_MVFR1_ASIMD_HPFP_MASK   0x00f00000
 
#define ARM_MVFR1_ASIMD_SPFP_MASK   0x000f0000
 
#define ARM_MVFR1_ASIMD_INT_MASK   0x0000f000
 
#define ARM_MVFR1_ASIMD_LDST_MASK   0x00000f00
 
#define ARM_MVFR1_D_NAN_MASK   0x000000f0
 
#define ARM_MVFR1_FTZ_MASK   0x0000000f
 
#define ARM3_CP15_FLUSH   1
 
#define ARM3_CP15_CONTROL   2
 
#define ARM3_CP15_CACHEABLE   3
 
#define ARM3_CP15_UPDATEABLE   4
 
#define ARM3_CP15_DISRUPTIVE   5
 
#define ARM3_CTL_CACHE_ON   0x00000001
 
#define ARM3_CTL_SHARED   0x00000002
 
#define ARM3_CTL_MONITOR   0x00000004
 
#define CPU_CONTROL_MMU_ENABLE   0x00000001 /* M: MMU/Protection unit enable */
 
#define CPU_CONTROL_AFLT_ENABLE   0x00000002 /* A: Alignment fault enable */
 
#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
 
#define CPU_CONTROL_WBUF_ENABLE   0x00000008 /* W: Write buffer enable */
 
#define CPU_CONTROL_32BP_ENABLE   0x00000010 /* P: 32-bit exception handlers */
 
#define CPU_CONTROL_32BD_ENABLE   0x00000020 /* D: 32-bit addressing */
 
#define CPU_CONTROL_LABT_ENABLE   0x00000040 /* L: Late abort enable */
 
#define CPU_CONTROL_BEND_ENABLE   0x00000080 /* B: Big-endian mode */
 
#define CPU_CONTROL_SYST_ENABLE   0x00000100 /* S: System protection bit */
 
#define CPU_CONTROL_ROM_ENABLE   0x00000200 /* R: ROM protection bit */
 
#define CPU_CONTROL_CPCLK   0x00000400 /* F: Implementation defined */
 
#define CPU_CONTROL_SWP_ENABLE   0x00000400 /* SW: SWP{B} perform normally. */
 
#define CPU_CONTROL_BPRD_ENABLE   0x00000800 /* Z: Branch prediction enable */
 
#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
 
#define CPU_CONTROL_VECRELOC   0x00002000 /* V: Vector relocation */
 
#define CPU_CONTROL_ROUNDROBIN   0x00004000 /* RR: Predictable replacement */
 
#define CPU_CONTROL_V4COMPAT   0x00008000 /* L4: ARMv4 compat LDR R15 etc */
 
#define CPU_CONTROL_HA_ENABLE   0x00020000 /* HA: Hardware Access flag enable */
 
#define CPU_CONTROL_WXN_ENABLE   0x00080000 /* WXN: Write Execute Never */
 
#define CPU_CONTROL_UWXN_ENABLE   0x00100000 /* UWXN: User Write eXecute Never */
 
#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
 
#define CPU_CONTROL_UNAL_ENABLE   0x00400000 /* U: unaligned data access */
 
#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
 
#define CPU_CONTROL_V_ENABLE   0x01000000 /* VE: Interrupt vectors enable */
 
#define CPU_CONTROL_EX_BEND   0x02000000 /* EE: exception endianness */
 
#define CPU_CONTROL_NMFI   0x08000000 /* NMFI: Non maskable FIQ */
 
#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
 
#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
 
#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
 
#define CPU_CONTROL_IDC_ENABLE   CPU_CONTROL_DC_ENABLE
 
#define CPACR_V7_ASEDIS   0x80000000 /* Disable Advanced SIMD Ext. */
 
#define CPACR_V7_D32DIS   0x40000000 /* Disable VFP regs 15-31 */
 
#define CPACR_CPn(n)   (3 << (2*n))
 
#define CPACR_NOACCESS   0 /* reset value */
 
#define CPACR_PRIVED   1 /* Privileged mode access */
 
#define CPACR_RESERVED   2
 
#define CPACR_ALL   3 /* Privileged and User mode access */
 
#define NSACR_SMP   0x00040000 /* ACTRL.SMP is writeable (!A8) */
 
#define NSACR_L2ERR   0x00020000 /* L2ECTRL is writeable (!A8) */
 
#define NSACR_ASEDIS   0x00008000 /* Deny Advanced SIMD Ext. */
 
#define NSACR_D32DIS   0x00004000 /* Deny VFP regs 15-31 */
 
#define NSACR_CPn(n)   (1 << (n)) /* NonSecure access allowed */
 
#define ARM11X6_AUXCTL_RS   0x00000001 /* return stack */
 
#define ARM11X6_AUXCTL_DB   0x00000002 /* dynamic branch prediction */
 
#define ARM11X6_AUXCTL_SB   0x00000004 /* static branch prediction */
 
#define ARM11X6_AUXCTL_TR   0x00000008 /* MicroTLB replacement strat. */
 
#define ARM11X6_AUXCTL_EX   0x00000010 /* exclusive L1/L2 cache */
 
#define ARM11X6_AUXCTL_RA   0x00000020 /* clean entire cache disable */
 
#define ARM11X6_AUXCTL_RV   0x00000040 /* block transfer cache disable */
 
#define ARM11X6_AUXCTL_CZ   0x00000080 /* restrict cache size */
 
#define ARM1136_AUXCTL_PFI   0x80000000 /* PFI: partial FI mode. */
 
#define ARM1176_AUXCTL_PHD   0x10000000 /* inst. prefetch halting disable */
 
#define ARM1176_AUXCTL_BFD   0x20000000 /* branch folding disable */
 
#define ARM1176_AUXCTL_FSD   0x40000000 /* force speculative ops disable */
 
#define ARM1176_AUXCTL_FIO   0x80000000 /* low intr latency override */
 
#define XSCALE_AUXCTL_K   0x00000001 /* dis. write buffer coalescing */
 
#define XSCALE_AUXCTL_P   0x00000002 /* ECC protect page table access */
 
#define XSCALE_AUXCTL_MD_WB_RA   0x00000000 /* mini-D$ wb, read-allocate */
 
#define XSCALE_AUXCTL_MD_WB_RWA   0x00000010 /* mini-D$ wb, read/write-allocate */
 
#define XSCALE_AUXCTL_MD_WT   0x00000020 /* mini-D$ wt, read-allocate */
 
#define XSCALE_AUXCTL_MD_MASK   0x00000030
 
#define MPCORE_AUXCTL_RS   0x00000001 /* return stack */
 
#define MPCORE_AUXCTL_DB   0x00000002 /* dynamic branch prediction */
 
#define MPCORE_AUXCTL_SB   0x00000004 /* static branch prediction */
 
#define MPCORE_AUXCTL_F   0x00000008 /* instruction folding enable */
 
#define MPCORE_AUXCTL_EX   0x00000010 /* exclusive L1/L2 cache */
 
#define MPCORE_AUXCTL_SA   0x00000020 /* SMP/AMP */
 
#define PJ4B_AUXCTL_FW   __BIT(0) /* Cache and TLB updates broadcast */
 
#define PJ4B_AUXCTL_SMPNAMP   __BIT(6) /* 0 = AMP, 1 = SMP */
 
#define PJ4B_AUXCTL_L1PARITY   __BIT(9) /* L1 parity checking */
 
#define PJ4B_AUXFMC0_L2EN   __BIT(0) /* Tightly-Coupled L2 cache enable */
 
#define PJ4B_AUXFMC0_SMPNAMP   __BIT(1) /* 0 = AMP, 1 = SMP */
 
#define PJ4B_AUXFMC0_L1PARITY   __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */
 
#define PJ4B_AUXFMC0_DCSLFD   __BIT(2) /* Disable DC Speculative linefill */
 
#define PJ4B_AUXFMC0_FW   __BIT(8) /* alias of PJ4B_AUXCTL_FW*/
 
#define CORTEXA5_ACTLR_FW   __BIT(0)
 
#define CORTEXA5_ACTLR_SMP   __BIT(6) /* Inner Cache Shared is cacheable */
 
#define CORTEXA5_ACTLR_EXCL   __BIT(7) /* Exclusive L1/L2 cache control */
 
#define CORTEXA7_ACTLR_L1ALIAS   __BIT(0) /* Enables L1 cache alias checks */
 
#define CORTEXA7_ACTLR_L2EN   __BIT(1) /* Enables L2 cache */
 
#define CORTEXA7_ACTLR_SMP   __BIT(6) /* SMP */
 
#define CORTEXA8_ACTLR_L1ALIAS   __BIT(0) /* Enables L1 cache alias checks */
 
#define CORTEXA8_ACTLR_L2EN   __BIT(1) /* Enables L2 cache */
 
#define CORTEXA9_AUXCTL_FW   0x00000001 /* Cache and TLB updates broadcast */
 
#define CORTEXA9_AUXCTL_L2PE   0x00000002 /* Prefetch hint enable */
 
#define CORTEXA9_AUXCTL_L1PE   0x00000004 /* Data prefetch hint enable */
 
#define CORTEXA9_AUXCTL_WR_ZERO   0x00000008 /* Ena. write full line of 0s mode */
 
#define CORTEXA9_AUXCTL_SMP   0x00000040 /* Coherency is active */
 
#define CORTEXA9_AUXCTL_EXCL   0x00000080 /* Exclusive cache bit */
 
#define CORTEXA9_AUXCTL_ONEWAY   0x00000100 /* Allocate in on cache way only */
 
#define CORTEXA9_AUXCTL_PARITY   0x00000200 /* Support parity checking */
 
#define CORTEXA15_ACTLR_BTB   __BIT(0) /* Cache and TLB updates broadcast */
 
#define CORTEXA15_ACTLR_SMP   __BIT(6) /* SMP */
 
#define CORTEXA15_ACTLR_IOBEU   __BIT(15) /* In order issue in Branch Exec Unit */
 
#define CORTEXA15_ACTLR_SDEH   __BIT(31) /* snoop-delayed exclusive handling */
 
#define FC_DCACHE_REPL_LOCK   0x80000000 /* Replace DCache Lock */
 
#define FC_DCACHE_STREAM_EN   0x20000000 /* DCache Streaming Switch */
 
#define FC_WR_ALLOC_EN   0x10000000 /* Enable Write Allocate */
 
#define FC_L2_PREF_DIS   0x01000000 /* L2 Cache Prefetch Disable */
 
#define FC_L2_INV_EVICT_LINE   0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
 
#define FC_L2CACHE_EN   0x00400000 /* L2 enable */
 
#define FC_ICACHE_REPL_LOCK   0x00080000 /* Replace ICache Lock */
 
#define FC_GLOB_HIST_REG_EN   0x00040000 /* Branch Global History Register Enable */
 
#define FC_BRANCH_TARG_BUF_DIS   0x00020000 /* Branch Target Buffer Disable */
 
#define FC_L1_PAR_ERR_EN   0x00010000 /* L1 Parity Error Enable */
 
#define CPU_CT_FORMAT(x)   (((x) >> 29) & 0x7) /* reg format */
 
#define CPU_CT_ISIZE(x)   ((x) & 0xfff) /* I$ info */
 
#define CPU_CT_DSIZE(x)   (((x) >> 12) & 0xfff) /* D$ info */
 
#define CPU_CT_S   (1U << 24) /* split cache */
 
#define CPU_CT_CTYPE(x)   (((x) >> 25) & 0xf) /* cache type */
 
#define CPU_CT_CTYPE_WT   0 /* write-through */
 
#define CPU_CT_CTYPE_WB1   1 /* write-back, clean w/ read */
 
#define CPU_CT_CTYPE_WB2   2 /* w/b, clean w/ cp15,7 */
 
#define CPU_CT_CTYPE_WB6   6 /* w/b, cp15,7, lockdown fmt A */
 
#define CPU_CT_CTYPE_WB7   7 /* w/b, cp15,7, lockdown fmt B */
 
#define CPU_CT_CTYPE_WB14   14 /* w/b, cp15,7, lockdown fmt C */
 
#define CPU_CT_xSIZE_LEN(x)   ((x) & 0x3) /* line size */
 
#define CPU_CT_xSIZE_M   (1U << 2) /* multiplier */
 
#define CPU_CT_xSIZE_ASSOC(x)   (((x) >> 3) & 0x7) /* associativity */
 
#define CPU_CT_xSIZE_SIZE(x)   (((x) >> 6) & 0x7) /* size */
 
#define CPU_CT_xSIZE_P   (1U << 11) /* need to page-color */
 
#define CPU_CT4_ILINE(x)   ((x) & 0xf) /* I$ line size */
 
#define CPU_CT4_DLINE(x)   (((x) >> 16) & 0xf) /* D$ line size */
 
#define CPU_CT4_L1IPOLICY(x)   (((x) >> 14) & 0x3) /* I$ policy */
 
#define CPU_CT4_L1_AIVIVT   1 /* ASID tagged VIVT */
 
#define CPU_CT4_L1_VIPT   2 /* VIPT */
 
#define CPU_CT4_L1_PIPT   3 /* PIPT */
 
#define CPU_CT4_ERG(x)   (((x) >> 20) & 0xf) /* Cache WriteBack Granule */
 
#define CPU_CT4_CWG(x)   (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */
 
#define CPU_CSID_CTYPE_WT   0x80000000 /* write-through avail */
 
#define CPU_CSID_CTYPE_WB   0x40000000 /* write-back avail */
 
#define CPU_CSID_CTYPE_RA   0x20000000 /* read-allocation avail */
 
#define CPU_CSID_CTYPE_WA   0x10000000 /* write-allocation avail */
 
#define CPU_CSID_NUMSETS(x)   (((x) >> 13) & 0x7fff)
 
#define CPU_CSID_ASSOC(x)   (((x) >> 3) & 0x1ff)
 
#define CPU_CSID_LEN(x)   ((x) & 0x07)
 
#define CPU_CSSR_L2   0x00000002
 
#define CPU_CSSR_L1   0x00000000
 
#define CPU_CSSR_InD   0x00000001
 
#define FAULT_TYPE_MASK   0x0f
 
#define FAULT_USER   0x10
 
#define FAULT_WRTBUF_0   0x00 /* Vector Exception */
 
#define FAULT_WRTBUF_1   0x02 /* Terminal Exception */
 
#define FAULT_BUSERR_0   0x04 /* External Abort on Linefetch -- Section */
 
#define FAULT_BUSERR_1   0x06 /* External Abort on Linefetch -- Page */
 
#define FAULT_BUSERR_2   0x08 /* External Abort on Non-linefetch -- Section */
 
#define FAULT_BUSERR_3   0x0a /* External Abort on Non-linefetch -- Page */
 
#define FAULT_BUSTRNL1   0x0c /* External abort on Translation -- Level 1 */
 
#define FAULT_BUSTRNL2   0x0e /* External abort on Translation -- Level 2 */
 
#define FAULT_ALIGN_0   0x01 /* Alignment */
 
#define FAULT_ALIGN_1   0x03 /* Alignment */
 
#define FAULT_TRANS_S   0x05 /* Translation -- Section */
 
#define FAULT_TRANS_P   0x07 /* Translation -- Page */
 
#define FAULT_DOMAIN_S   0x09 /* Domain -- Section */
 
#define FAULT_DOMAIN_P   0x0b /* Domain -- Page */
 
#define FAULT_PERM_S   0x0d /* Permission -- Section */
 
#define FAULT_PERM_P   0x0f /* Permission -- Page */
 
#define FAULT_LPAE   0x0200 /* (SW) used long descriptors */
 
#define FAULT_IMPRECISE   0x0400 /* Imprecise exception (XSCALE) */
 
#define FAULT_WRITE   0x0800 /* fault was due to write (ARMv6+) */
 
#define FAULT_EXT   0x1000 /* fault was due to external abort (ARMv6+) */
 
#define FAULT_CM   0x2000 /* fault was due to cache maintenance (ARMv7+) */
 
#define ARM_VECTORS_LOW   0x00000000U
 
#define ARM_VECTORS_HIGH   0xffff0000U
 
#define INSN_SIZE   4 /* Always 4 bytes */
 
#define INSN_COND_MASK   0xf0000000 /* Condition mask */
 
#define INSN_COND_EQ   0 /* Z == 1 */
 
#define INSN_COND_NE   1 /* Z == 0 */
 
#define INSN_COND_CS   2 /* C == 1 */
 
#define INSN_COND_CC   3 /* C == 0 */
 
#define INSN_COND_MI   4 /* N == 1 */
 
#define INSN_COND_PL   5 /* N == 0 */
 
#define INSN_COND_VS   6 /* V == 1 */
 
#define INSN_COND_VC   7 /* V == 0 */
 
#define INSN_COND_HI   8 /* C == 1 && Z == 0 */
 
#define INSN_COND_LS   9 /* C == 0 || Z == 1 */
 
#define INSN_COND_GE   10 /* N == V */
 
#define INSN_COND_LT   11 /* N != V */
 
#define INSN_COND_GT   12 /* Z == 0 && N == V */
 
#define INSN_COND_LE   13 /* Z == 1 || N != V */
 
#define INSN_COND_AL   14 /* Always condition */
 
#define THUMB_INSN_SIZE   2 /* Some are 4 bytes. */
 
#define ARM11_PMCCTL_E   __BIT(0) /* enable all three counters */
 
#define ARM11_PMCCTL_P   __BIT(1) /* reset both Count Registers to zero */
 
#define ARM11_PMCCTL_C   __BIT(2) /* reset the Cycle Counter Register to zero */
 
#define ARM11_PMCCTL_D   __BIT(3) /* cycle count divide by 64 */
 
#define ARM11_PMCCTL_EC0   __BIT(4) /* Enable Counter Register 0 interrupt */
 
#define ARM11_PMCCTL_EC1   __BIT(5) /* Enable Counter Register 1 interrupt */
 
#define ARM11_PMCCTL_ECC   __BIT(6) /* Enable Cycle Counter interrupt */
 
#define ARM11_PMCCTL_SBZa   __BIT(7) /* UNP/SBZ */
 
#define ARM11_PMCCTL_CR0   __BIT(8) /* Count Register 0 overflow flag */
 
#define ARM11_PMCCTL_CR1   __BIT(9) /* Count Register 1 overflow flag */
 
#define ARM11_PMCCTL_CCR   __BIT(10) /* Cycle Count Register overflow flag */
 
#define ARM11_PMCCTL_X   __BIT(11) /* Enable Export of the events to the event bus */
 
#define ARM11_PMCCTL_EVT1   __BITS(19,12) /* source of events for Count Register 1 */
 
#define ARM11_PMCCTL_EVT0   __BITS(27,20) /* source of events for Count Register 0 */
 
#define ARM11_PMCCTL_SBZb   __BITS(31,28) /* UNP/SBZ */
 
#define ARM11_PMCCTL_SBZ   (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb)
 
#define ARM11_PMCEVT_ICACHE_MISS   0 /* Instruction Cache Miss */
 
#define ARM11_PMCEVT_ISTREAM_STALL   1 /* Instruction Stream Stall */
 
#define ARM11_PMCEVT_IUTLB_MISS   2 /* Instruction uTLB Miss */
 
#define ARM11_PMCEVT_DUTLB_MISS   3 /* Data uTLB Miss */
 
#define ARM11_PMCEVT_BRANCH   4 /* Branch Inst. Executed */
 
#define ARM11_PMCEVT_BRANCH_MISS   6 /* Branch mispredicted */
 
#define ARM11_PMCEVT_INST_EXEC   7 /* Instruction Executed */
 
#define ARM11_PMCEVT_DCACHE_ACCESS0   9 /* Data Cache Access */
 
#define ARM11_PMCEVT_DCACHE_ACCESS1   10 /* Data Cache Access */
 
#define ARM11_PMCEVT_DCACHE_MISS   11 /* Data Cache Miss */
 
#define ARM11_PMCEVT_DCACHE_WRITEBACK   12 /* Data Cache Writeback */
 
#define ARM11_PMCEVT_PC_CHANGE   13 /* Software PC change */
 
#define ARM11_PMCEVT_TLB_MISS   15 /* Main TLB Miss */
 
#define ARM11_PMCEVT_DATA_ACCESS   16 /* non-cached data access */
 
#define ARM11_PMCEVT_LSU_STALL   17 /* Load/Store Unit stall */
 
#define ARM11_PMCEVT_WBUF_DRAIN   18 /* Write buffer drained */
 
#define ARM11_PMCEVT_ETMEXTOUT0   32 /* ETMEXTOUT[0] asserted */
 
#define ARM11_PMCEVT_ETMEXTOUT1   33 /* ETMEXTOUT[1] asserted */
 
#define ARM11_PMCEVT_ETMEXTOUT   34 /* ETMEXTOUT[0 & 1] */
 
#define ARM11_PMCEVT_CALL_EXEC   35 /* Procedure call executed */
 
#define ARM11_PMCEVT_RETURN_EXEC   36 /* Return executed */
 
#define ARM11_PMCEVT_RETURN_HIT   37 /* return address predicted */
 
#define ARM11_PMCEVT_RETURN_MISS   38 /* return addr. mispredicted */
 
#define ARM11_PMCEVT_CYCLE   255 /* Increment each cycle */
 
#define CORTEX_CNTENS_C   __BIT(31) /* Enables the cycle counter */
 
#define CORTEX_CNTENC_C   __BIT(31) /* Disables the cycle counter */
 
#define CORTEX_CNTOFL_C   __BIT(31) /* Cycle counter overflow flag */
 
#define L2CTRL_NUMCPU   __BITS(25,24)
 
#define L2CTRL_ICPRES   __BIT(23)
 
#define TTBR_C   __BIT(0) /* without MPE */
 
#define TTBR_S   __BIT(1)
 
#define TTBR_IMP   __BIT(2)
 
#define TTBR_RGN_MASK   __BITS(4,3)
 
#define TTBR_RGN_NC   __SHIFTIN(0, TTBR_RGN_MASK)
 
#define TTBR_RGN_WBWA   __SHIFTIN(1, TTBR_RGN_MASK)
 
#define TTBR_RGN_WT   __SHIFTIN(2, TTBR_RGN_MASK)
 
#define TTBR_RGN_WBNWA   __SHIFTIN(3, TTBR_RGN_MASK)
 
#define TTBR_NOS   __BIT(5)
 
#define TTBR_IRGN_MASK   (__BIT(6) | __BIT(0))
 
#define TTBR_IRGN_NC   0
 
#define TTBR_IRGN_WBWA   __BIT(6)
 
#define TTBR_IRGN_WT   __BIT(0)
 
#define TTBR_IRGN_WBNWA   (__BIT(0) | __BIT(6))
 
#define TTBCR_S_EAE   __BIT(31)
 
#define TTBCR_S_PD1   __BIT(5)
 
#define TTBCR_S_PD0   __BIT(4)
 
#define TTBCR_S_N   __BITS(2,0)
 
#define TTBCR_L_EAE   __BIT(31)
 
#define TTBCR_L_SH1   __BITS(29,28)
 
#define TTBCR_L_ORGN1   __BITS(27,26)
 
#define TTBCR_L_IRGN1   __BITS(25,24)
 
#define TTBCR_L_EPD1   __BIT(23)
 
#define TTBCR_L_A1   __BIT(22)
 
#define TTBCR_L_T1SZ   __BITS(18,16)
 
#define TTBCR_L_SH0   __BITS(13,12)
 
#define TTBCR_L_ORGN0   __BITS(11,10)
 
#define TTBCR_L_IRGN0   __BITS(9,8)
 
#define TTBCR_L_EPD0   __BIT(7)
 
#define TTBCR_L_T0SZ   __BITS(2,0)
 
#define NRRR_ORn(n)   __BITS(17+2*(n),16+2*(n))
 
#define NRRR_IRn(n)   __BITS(1+2*(n),0+2*(n))
 
#define NRRR_NC   0
 
#define NRRR_WB_WA   1
 
#define NRRR_WT   2
 
#define NRRR_WB   3
 
#define PRRR_NOSn(n)   __BITS(24+2*(n))
 
#define PRRR_NS1   __BIT(19)
 
#define PRRR_NS0   __BIT(18)
 
#define PRRR_DS1   __BIT(17)
 
#define PRRR_DS0   __BIT(16)
 
#define PRRR_TRn(n)   __BITS(1+2*(n),0+2*(n))
 
#define PRRR_TR_STRONG   0
 
#define PRRR_TR_DEVICE   1
 
#define PRRR_TR_NORMAL   2
 
#define MPIDR_MP   __BIT(31) /* 1 = Have MP Extention */
 
#define MPIDR_U   __BIT(30) /* 1 = Uni-Processor System */
 
#define MPIDR_MT   __BIT(24) /* 1 = SMT(AFF0 is logical) */
 
#define MPIDR_AFF2   __BITS(23,16) /* Affinity Level 2 */
 
#define MPIDR_AFF1   __BITS(15,8) /* Affinity Level 1 */
 
#define MPIDR_AFF0   __BITS(7,0) /* Affinity Level 0 */
 
#define CORTEXA9_MPIDR_MP   MPIDR_MP
 
#define CORTEXA9_MPIDR_U   MPIDR_U
 
#define CORTEXA9_MPIDR_CLID   __BITS(11,8) /* AFF1 = cluster id */
 
#define CORTEXA9_MPIDR_CPUID   __BITS(0,1) /* AFF0 = physical core id */
 
#define PJ4B_MPIDR_MP   MPIDR_MP
 
#define PJ4B_MPIDR_U   MPIDR_U
 
#define PJ4B_MPIDR_MT   MPIDR_MT /* 1 = SMT(AFF0 is logical) */
 
#define PJ4B_MPIDR_CLID   __BITS(11,8) /* AFF1 = cluster id */
 
#define PJ4B_MPIDR_CPUID   __BITS(0,3) /* AFF0 = core id */
 
#define CNTCTL_ISTATUS   __BIT(2)
 
#define CNTCTL_IMASK   __BIT(1)
 
#define CNTCTL_ENABLE   __BIT(0)
 
#define CNTKCTL_PL0PTEN   __BIT(9) /* PL0 Physical Timer Enable */
 
#define CNTKCTL_PL0VTEN   __BIT(8) /* PL0 Virtual Timer Enable */
 
#define CNTKCTL_EVNTI   __BITS(7,4) /* CNTVCT Event Bit Select */
 
#define CNTKCTL_EVNTDIR   __BIT(3) /* CNTVCT Event Dir (1->0) */
 
#define CNTKCTL_EVNTEN   __BIT(2) /* CNTVCT Event Enable */
 
#define CNTKCTL_PL0VCTEN   __BIT(1) /* PL0 Virtual Counter Enable */
 
#define CNTKCTL_PL0PCTEN   __BIT(0) /* PL0 Physical Counter Enable */
 
#define CNTHCTL_EVNTI   __BITS(7,4)
 
#define CNTHCTL_EVNTDIR   __BIT(3)
 
#define CNTHCTL_EVNTEN   __BIT(2)
 
#define CNTHCTL_PL1PCEN   __BIT(1)
 
#define CNTHCTL_PL1PCTEN   __BIT(0)
 
#define ARM_A5_TLBDATA_DOM   __BITS(62,59)
 
#define ARM_A5_TLBDATA_AP   __BITS(58,56)
 
#define ARM_A5_TLBDATA_NS_WALK   __BIT(55)
 
#define ARM_A5_TLBDATA_NS_PAGE   __BIT(54)
 
#define ARM_A5_TLBDATA_XN   __BIT(53)
 
#define ARM_A5_TLBDATA_TEX   __BITS(52,50)
 
#define ARM_A5_TLBDATA_B   __BIT(49)
 
#define ARM_A5_TLBDATA_C   __BIT(48)
 
#define ARM_A5_TLBDATA_S   __BIT(47)
 
#define ARM_A5_TLBDATA_ASID   __BITS(46,39)
 
#define ARM_A5_TLBDATA_SIZE   __BITS(38,37)
 
#define ARM_A5_TLBDATA_SIZE_4KB   0
 
#define ARM_A5_TLBDATA_SIZE_16KB   1
 
#define ARM_A5_TLBDATA_SIZE_1MB   2
 
#define ARM_A5_TLBDATA_SIZE_16MB   3
 
#define ARM_A5_TLBDATA_VA   __BITS(36,22)
 
#define ARM_A5_TLBDATA_PA   __BITS(21,2)
 
#define ARM_A5_TLBDATA_nG   __BIT(1)
 
#define ARM_A5_TLBDATA_VALID   __BIT(0)
 
#define ARM_A7_TLBDATA2_S2_LEVEL   __BITS(85-64,84-64)
 
#define ARM_A7_TLBDATA2_S1_SIZE   __BITS(83-64,82-64)
 
#define ARM_A7_TLBDATA2_S1_SIZE_4KB   0
 
#define ARM_A7_TLBDATA2_S1_SIZE_64KB   1
 
#define ARM_A7_TLBDATA2_S1_SIZE_1MB   2
 
#define ARM_A7_TLBDATA2_S1_SIZE_16MB   3
 
#define ARM_A7_TLBDATA2_DOM   __BITS(81-64,78-64)
 
#define ARM_A7_TLBDATA2_IS   __BITS(77-64,76-64)
 
#define ARM_A7_TLBDATA2_IS_NC   0
 
#define ARM_A7_TLBDATA2_IS_WB_WA   1
 
#define ARM_A7_TLBDATA2_IS_WT   2
 
#define ARM_A7_TLBDATA2_IS_DSO   3
 
#define ARM_A7_TLBDATA2_S2OVR   __BIT(75-64)
 
#define ARM_A7_TLBDATA2_SDO_MT   __BITS(74-64,72-64)
 
#define ARM_A7_TLBDATA2_SDO_MT_D   2
 
#define ARM_A7_TLBDATA2_SDO_MT_SO   6
 
#define ARM_A7_TLBDATA2_OS   __BITS(75-64,74-64)
 
#define ARM_A7_TLBDATA2_OS_NC   0
 
#define ARM_A7_TLBDATA2_OS_WB_WA   1
 
#define ARM_A7_TLBDATA2_OS_WT   2
 
#define ARM_A7_TLBDATA2_OS_WB   3
 
#define ARM_A7_TLBDATA2_SH   __BITS(73-64,72-64)
 
#define ARM_A7_TLBDATA2_SH_NONE   0
 
#define ARM_A7_TLBDATA2_SH_UNUSED   1
 
#define ARM_A7_TLBDATA2_SH_OS   2
 
#define ARM_A7_TLBDATA2_SH_IS   3
 
#define ARM_A7_TLBDATA2_XN2   __BIT(71-64)
 
#define ARM_A7_TLBDATA2_XN1   __BIT(70-64)
 
#define ARM_A7_TLBDATA2_PXN   __BIT(69-64)
 
#define ARM_A7_TLBDATA12_PA   __BITS(68-32,41-32)
 
#define ARM_A7_TLBDATA1_NS   __BIT(40-32)
 
#define ARM_A7_TLBDATA1_HAP   __BITS(39-32,38-32)
 
#define ARM_A7_TLBDATA1_AP   __BITS(37-32,35-32)
 
#define ARM_A7_TLBDATA1_nG   __BIT(34-32)
 
#define ARM_A7_TLBDATA01_ASID   __BITS(33,26)
 
#define ARM_A7_TLBDATA0_VMID   __BITS(25,18)
 
#define ARM_A7_TLBDATA0_VA   __BITS(17,5)
 
#define ARM_A7_TLBDATA0_NS_WALK   __BIT(4)
 
#define ARM_A7_TLBDATA0_SIZE   __BITS(3,1)
 
#define ARM_A7_TLBDATA0_SIZE_V7_4KB   0
 
#define ARM_A7_TLBDATA0_SIZE_LPAE_4KB   1
 
#define ARM_A7_TLBDATA0_SIZE_V7_64KB   2
 
#define ARM_A7_TLBDATA0_SIZE_LPAE_64KB   3
 
#define ARM_A7_TLBDATA0_SIZE_V7_1MB   4
 
#define ARM_A7_TLBDATA0_SIZE_LPAE_2MB   5
 
#define ARM_A7_TLBDATA0_SIZE_V7_16MB   6
 
#define ARM_A7_TLBDATA0_SIZE_LPAE_1GB   7
 
#define ARM_TLBDATA_VALID   __BIT(0)
 
#define ARM_TLBDATAOP_WAY   __BIT(31)
 
#define ARM_A5_TLBDATAOP_INDEX   __BITS(5,0)
 
#define ARM_A7_TLBDATAOP_INDEX   __BITS(6,0)
 
#define ARMREG_READ_INLINE(name, __insnstring)
 
#define ARMREG_WRITE_INLINE(name, __insnstring)
 
#define ARMREG_READ_INLINE2(name, __insnstring)
 
#define ARMREG_WRITE_INLINE2(name, __insnstring)
 
#define ARMREG_READ64_INLINE(name, __insnstring)
 
#define ARMREG_WRITE64_INLINE(name, __insnstring)
 

Functions

 ARMREG_READ_INLINE2 (fpsid, "vmrs\t%0, fpsid") ARMREG_READ_INLINE2(fpscr
 
vmrs fpscr ARMREG_WRITE_INLINE2 (fpscr, "vmsr\tfpscr, %0") ARMREG_READ_INLINE2(mvfr1
 
vmrs fpscr vmrs mvfr1 ARMREG_READ_INLINE2 (mvfr0, "vmrs\t%0, mvfr0") ARMREG_READ_INLINE2(fpexc
 
vmrs fpscr vmrs mvfr1 vmrs fpexc ARMREG_WRITE_INLINE2 (fpexc, "vmsr\tfpexc, %0") ARMREG_READ_INLINE2(fpinst
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst ARMREG_WRITE_INLINE2 (fpinst, "fmxr\tfpinst, %0") ARMREG_READ_INLINE2(fpinst2
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE2 (fpinst2, "fmxr\tfpinst2, %0") ARMREG_READ_INLINE(midr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (ctr, "p15,0,%0,c0,c0,1") ARMREG_READ_INLINE(tlbtr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (mpidr, "p15,0,%0,c0,c0,5") ARMREG_READ_INLINE(revidr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (pfr0, "p15,0,%0,c0,c1,0") ARMREG_READ_INLINE(pfr1
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (mmfr0, "p15,0,%0,c0,c1,4") ARMREG_READ_INLINE(mmfr1
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (mmfr2, "p15,0,%0,c0,c1,6") ARMREG_READ_INLINE(mmfr3
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (isar0, "p15,0,%0,c0,c2,0") ARMREG_READ_INLINE(isar1
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (isar2, "p15,0,%0,c0,c2,2") ARMREG_READ_INLINE(isar3
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (isar4, "p15,0,%0,c0,c2,4") ARMREG_READ_INLINE(isar5
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (ccsidr, "p15,1,%0,c0,c0,0") ARMREG_READ_INLINE(clidr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (csselr, "p15,2,%0,c0,c0,0") ARMREG_WRITE_INLINE(csselr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (sctlr, "p15,0,%0,c1,c0,0") ARMREG_WRITE_INLINE(sctlr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (auxctl, "p15,0,%0,c1,c0,1") ARMREG_WRITE_INLINE(auxctl
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cpacr, "p15,0,%0,c1,c0,2") ARMREG_WRITE_INLINE(cpacr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (scr, "p15,0,%0,c1,c1,0") ARMREG_READ_INLINE(nsacr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (ttbr, "p15,0,%0,c2,c0,0") ARMREG_WRITE_INLINE(ttbr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (ttbr1, "p15,0,%0,c2,c0,1") ARMREG_WRITE_INLINE(ttbr1
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (ttbcr, "p15,0,%0,c2,c0,2") ARMREG_WRITE_INLINE(ttbcr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (dacr, "p15,0,%0,c3,c0,0") ARMREG_WRITE_INLINE(dacr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (dfsr, "p15,0,%0,c5,c0,0") ARMREG_READ_INLINE(ifsr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (dfar, "p15,0,%0,c6,c0,0") ARMREG_READ_INLINE(ifar
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (icialluis, "p15,0,%0,c7,c1,0") ARMREG_WRITE_INLINE(bpiallis
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (par, "p15,0,%0,c7,c4,0") ARMREG_WRITE_INLINE(iciallu
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (icimvau, "p15,0,%0,c7,c5,1") ARMREG_WRITE_INLINE(isb
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (bpiall, "p15,0,%0,c7,c5,6") ARMREG_WRITE_INLINE(bpimva
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dcimvac, "p15,0,%0,c7,c6,1") ARMREG_WRITE_INLINE(dcisw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (ats1cpr, "p15,0,%0,c7,c8,0") ARMREG_WRITE_INLINE(ats1cpw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (ats1cur, "p15,0,%0,c7,c8,2") ARMREG_WRITE_INLINE(ats1cuw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dccmvac, "p15,0,%0,c7,c10,1") ARMREG_WRITE_INLINE(dccsw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dsb, "p15,0,%0,c7,c10,4") ARMREG_WRITE_INLINE(dmb
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dccmvau, "p15,0,%0,c7,c11,1") ARMREG_WRITE_INLINE(dccimvac
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dccisw, "p15,0,%0,c7,c14,2") ARMREG_WRITE_INLINE(tlbiallis
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (tlbimvais, "p15,0,%0,c8,c3,1") ARMREG_WRITE_INLINE(tlbiasidis
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (tlbimvaais, "p15,0,%0,c8,c3,3") ARMREG_WRITE_INLINE(itlbiall
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (itlbimva, "p15,0,%0,c8,c5,1") ARMREG_WRITE_INLINE(itlbiasid
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dtlbiall, "p15,0,%0,c8,c6,0") ARMREG_WRITE_INLINE(dtlbimva
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (dtlbiasid, "p15,0,%0,c8,c6,2") ARMREG_WRITE_INLINE(tlbiall
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (tlbimva, "p15,0,%0,c8,c7,1") ARMREG_WRITE_INLINE(tlbiasid
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (tlbimvaa, "p15,0,%0,c8,c7,3") ARMREG_READ_INLINE(pmcr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmcr, "p15,0,%0,c9,c12,0") ARMREG_READ_INLINE(pmcntenset
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmcntenset, "p15,0,%0,c9,c12,1") ARMREG_READ_INLINE(pmcntenclr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmcntenclr, "p15,0,%0,c9,c12,2") ARMREG_READ_INLINE(pmovsr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmovsr, "p15,0,%0,c9,c12,3") ARMREG_READ_INLINE(pmselr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmselr, "p15,0,%0,c9,c12,5") ARMREG_READ_INLINE(pmceid0
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (pmceid1, "p15,0,%0,c9,c12,7") ARMREG_READ_INLINE(pmccntr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmccntr, "p15,0,%0,c9,c13,0") ARMREG_READ_INLINE(pmxevtyper
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmxevtyper, "p15,0,%0,c9,c13,1") ARMREG_READ_INLINE(pmxevcntr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmxevcntr, "p15,0,%0,c9,c13,2") ARMREG_READ_INLINE(pmuserenr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmuserenr, "p15,0,%0,c9,c14,0") ARMREG_READ_INLINE(pmintenset
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmintenset, "p15,0,%0,c9,c14,1") ARMREG_READ_INLINE(pmintenclr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE (pmintenclr, "p15,0,%0,c9,c14,2") ARMREG_READ_INLINE(l2ctrl
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (prrr, "p15,0,%0,c10,c2,0") ARMREG_WRITE_INLINE(prrr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (nrrr, "p15,0,%0,c10,c2,1") ARMREG_WRITE_INLINE(nrrr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (contextidr, "p15,0,%0,c13,c0,1") ARMREG_WRITE_INLINE(contextidr
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (tpidrurw, "p15,0,%0,c13,c0,2") ARMREG_WRITE_INLINE(tpidrurw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (tpidruro, "p15,0,%0,c13,c0,3") ARMREG_WRITE_INLINE(tpidruro
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (tpidrprw, "p15,0,%0,c13,c0,4") ARMREG_WRITE_INLINE(tpidrprw
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (vbar, "p15,0,%0,c12,c0,0") ARMREG_WRITE_INLINE(vbar
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cnt_frq, "p15,0,%0,c14,c0,0") ARMREG_WRITE_INLINE(cnt_frq
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cntk_ctl, "p15,0,%0,c14,c1,0") ARMREG_WRITE_INLINE(cntk_ctl
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cntp_tval, "p15,0,%0,c14,c2,0") ARMREG_WRITE_INLINE(cntp_tval
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cntp_ctl, "p15,0,%0,c14,c2,1") ARMREG_WRITE_INLINE(cntp_ctl
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cntv_tval, "p15,0,%0,c14,c3,0") ARMREG_WRITE_INLINE(cntv_tval
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE (cntv_ctl, "p15,0,%0,c14,c3,1") ARMREG_WRITE_INLINE(cntv_ctl
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ64_INLINE (cntp_ct, "p15,0,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntp_ct
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 ARMREG_READ64_INLINE (cntv_ct, "p15,1,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntv_ct
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 ARMREG_READ64_INLINE (cntp_cval, "p15,2,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntp_cval
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 ARMREG_READ64_INLINE (cntv_cval, "p15,3,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntv_cval
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 ARMREG_READ64_INLINE (cntvoff, "p15,4,%Q0,%R0,c14") ARMREG_WRITE64_INLINE(cntvoff
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_READ_INLINE (cbar, "p15,4,%0,c15,c0,0") ARMREG_READ_INLINE(pmcrv6
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE (pmcrv6, "p15,0,%0,c15,c12,0") ARMREG_READ_INLINE(pmccntrv6
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE (pmccntrv6, "p15,0,%0,c15,c12,1") ARMREG_READ_INLINE(tlbdata0
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_READ_INLINE (tlbdata1, "p15,3,%0,c15,c0,1") ARMREG_READ_INLINE(tlbdata2
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE (tlbdataop, "p15,3,%0,c15,c4,2") ARMREG_READ_INLINE(sheeva_xctrl
 

Variables

vmrs t
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 p15
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c0
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c1
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c2
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c3
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c5
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c6
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c7
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c8
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c10
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c9
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c12
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c13
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 Q0
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 R0
 
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 c15
 

Macro Definition Documentation

◆ ARM1136_AUXCTL_PFI

#define ARM1136_AUXCTL_PFI   0x80000000 /* PFI: partial FI mode. */

Definition at line 246 of file armreg.h.

◆ ARM1176_AUXCTL_BFD

#define ARM1176_AUXCTL_BFD   0x20000000 /* branch folding disable */

Definition at line 254 of file armreg.h.

◆ ARM1176_AUXCTL_FIO

#define ARM1176_AUXCTL_FIO   0x80000000 /* low intr latency override */

Definition at line 256 of file armreg.h.

◆ ARM1176_AUXCTL_FSD

#define ARM1176_AUXCTL_FSD   0x40000000 /* force speculative ops disable */

Definition at line 255 of file armreg.h.

◆ ARM1176_AUXCTL_PHD

#define ARM1176_AUXCTL_PHD   0x10000000 /* inst. prefetch halting disable */

Definition at line 253 of file armreg.h.

◆ ARM11_PMCCTL_C

#define ARM11_PMCCTL_C   __BIT(2) /* reset the Cycle Counter Register to zero */

Definition at line 442 of file armreg.h.

◆ ARM11_PMCCTL_CCR

#define ARM11_PMCCTL_CCR   __BIT(10) /* Cycle Count Register overflow flag */

Definition at line 450 of file armreg.h.

◆ ARM11_PMCCTL_CR0

#define ARM11_PMCCTL_CR0   __BIT(8) /* Count Register 0 overflow flag */

Definition at line 448 of file armreg.h.

◆ ARM11_PMCCTL_CR1

#define ARM11_PMCCTL_CR1   __BIT(9) /* Count Register 1 overflow flag */

Definition at line 449 of file armreg.h.

◆ ARM11_PMCCTL_D

#define ARM11_PMCCTL_D   __BIT(3) /* cycle count divide by 64 */

Definition at line 443 of file armreg.h.

◆ ARM11_PMCCTL_E

#define ARM11_PMCCTL_E   __BIT(0) /* enable all three counters */

Definition at line 440 of file armreg.h.

◆ ARM11_PMCCTL_EC0

#define ARM11_PMCCTL_EC0   __BIT(4) /* Enable Counter Register 0 interrupt */

Definition at line 444 of file armreg.h.

◆ ARM11_PMCCTL_EC1

#define ARM11_PMCCTL_EC1   __BIT(5) /* Enable Counter Register 1 interrupt */

Definition at line 445 of file armreg.h.

◆ ARM11_PMCCTL_ECC

#define ARM11_PMCCTL_ECC   __BIT(6) /* Enable Cycle Counter interrupt */

Definition at line 446 of file armreg.h.

◆ ARM11_PMCCTL_EVT0

#define ARM11_PMCCTL_EVT0   __BITS(27,20) /* source of events for Count Register 0 */

Definition at line 453 of file armreg.h.

◆ ARM11_PMCCTL_EVT1

#define ARM11_PMCCTL_EVT1   __BITS(19,12) /* source of events for Count Register 1 */

Definition at line 452 of file armreg.h.

◆ ARM11_PMCCTL_P

#define ARM11_PMCCTL_P   __BIT(1) /* reset both Count Registers to zero */

Definition at line 441 of file armreg.h.

◆ ARM11_PMCCTL_SBZ

#define ARM11_PMCCTL_SBZ   (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb)

Definition at line 455 of file armreg.h.

◆ ARM11_PMCCTL_SBZa

#define ARM11_PMCCTL_SBZa   __BIT(7) /* UNP/SBZ */

Definition at line 447 of file armreg.h.

◆ ARM11_PMCCTL_SBZb

#define ARM11_PMCCTL_SBZb   __BITS(31,28) /* UNP/SBZ */

Definition at line 454 of file armreg.h.

◆ ARM11_PMCCTL_X

#define ARM11_PMCCTL_X   __BIT(11) /* Enable Export of the events to the event bus */

Definition at line 451 of file armreg.h.

◆ ARM11_PMCEVT_BRANCH

#define ARM11_PMCEVT_BRANCH   4 /* Branch Inst. Executed */

Definition at line 462 of file armreg.h.

◆ ARM11_PMCEVT_BRANCH_MISS

#define ARM11_PMCEVT_BRANCH_MISS   6 /* Branch mispredicted */

Definition at line 463 of file armreg.h.

◆ ARM11_PMCEVT_CALL_EXEC

#define ARM11_PMCEVT_CALL_EXEC   35 /* Procedure call executed */

Definition at line 477 of file armreg.h.

◆ ARM11_PMCEVT_CYCLE

#define ARM11_PMCEVT_CYCLE   255 /* Increment each cycle */

Definition at line 481 of file armreg.h.

◆ ARM11_PMCEVT_DATA_ACCESS

#define ARM11_PMCEVT_DATA_ACCESS   16 /* non-cached data access */

Definition at line 471 of file armreg.h.

◆ ARM11_PMCEVT_DCACHE_ACCESS0

#define ARM11_PMCEVT_DCACHE_ACCESS0   9 /* Data Cache Access */

Definition at line 465 of file armreg.h.

◆ ARM11_PMCEVT_DCACHE_ACCESS1

#define ARM11_PMCEVT_DCACHE_ACCESS1   10 /* Data Cache Access */

Definition at line 466 of file armreg.h.

◆ ARM11_PMCEVT_DCACHE_MISS

#define ARM11_PMCEVT_DCACHE_MISS   11 /* Data Cache Miss */

Definition at line 467 of file armreg.h.

◆ ARM11_PMCEVT_DCACHE_WRITEBACK

#define ARM11_PMCEVT_DCACHE_WRITEBACK   12 /* Data Cache Writeback */

Definition at line 468 of file armreg.h.

◆ ARM11_PMCEVT_DUTLB_MISS

#define ARM11_PMCEVT_DUTLB_MISS   3 /* Data uTLB Miss */

Definition at line 461 of file armreg.h.

◆ ARM11_PMCEVT_ETMEXTOUT

#define ARM11_PMCEVT_ETMEXTOUT   34 /* ETMEXTOUT[0 & 1] */

Definition at line 476 of file armreg.h.

◆ ARM11_PMCEVT_ETMEXTOUT0

#define ARM11_PMCEVT_ETMEXTOUT0   32 /* ETMEXTOUT[0] asserted */

Definition at line 474 of file armreg.h.

◆ ARM11_PMCEVT_ETMEXTOUT1

#define ARM11_PMCEVT_ETMEXTOUT1   33 /* ETMEXTOUT[1] asserted */

Definition at line 475 of file armreg.h.

◆ ARM11_PMCEVT_ICACHE_MISS

#define ARM11_PMCEVT_ICACHE_MISS   0 /* Instruction Cache Miss */

Definition at line 458 of file armreg.h.

◆ ARM11_PMCEVT_INST_EXEC

#define ARM11_PMCEVT_INST_EXEC   7 /* Instruction Executed */

Definition at line 464 of file armreg.h.

◆ ARM11_PMCEVT_ISTREAM_STALL

#define ARM11_PMCEVT_ISTREAM_STALL   1 /* Instruction Stream Stall */

Definition at line 459 of file armreg.h.

◆ ARM11_PMCEVT_IUTLB_MISS

#define ARM11_PMCEVT_IUTLB_MISS   2 /* Instruction uTLB Miss */

Definition at line 460 of file armreg.h.

◆ ARM11_PMCEVT_LSU_STALL

#define ARM11_PMCEVT_LSU_STALL   17 /* Load/Store Unit stall */

Definition at line 472 of file armreg.h.

◆ ARM11_PMCEVT_PC_CHANGE

#define ARM11_PMCEVT_PC_CHANGE   13 /* Software PC change */

Definition at line 469 of file armreg.h.

◆ ARM11_PMCEVT_RETURN_EXEC

#define ARM11_PMCEVT_RETURN_EXEC   36 /* Return executed */

Definition at line 478 of file armreg.h.

◆ ARM11_PMCEVT_RETURN_HIT

#define ARM11_PMCEVT_RETURN_HIT   37 /* return address predicted */

Definition at line 479 of file armreg.h.

◆ ARM11_PMCEVT_RETURN_MISS

#define ARM11_PMCEVT_RETURN_MISS   38 /* return addr. mispredicted */

Definition at line 480 of file armreg.h.

◆ ARM11_PMCEVT_TLB_MISS

#define ARM11_PMCEVT_TLB_MISS   15 /* Main TLB Miss */

Definition at line 470 of file armreg.h.

◆ ARM11_PMCEVT_WBUF_DRAIN

#define ARM11_PMCEVT_WBUF_DRAIN   18 /* Write buffer drained */

Definition at line 473 of file armreg.h.

◆ ARM11X6_AUXCTL_CZ

#define ARM11X6_AUXCTL_CZ   0x00000080 /* restrict cache size */

Definition at line 243 of file armreg.h.

◆ ARM11X6_AUXCTL_DB

#define ARM11X6_AUXCTL_DB   0x00000002 /* dynamic branch prediction */

Definition at line 237 of file armreg.h.

◆ ARM11X6_AUXCTL_EX

#define ARM11X6_AUXCTL_EX   0x00000010 /* exclusive L1/L2 cache */

Definition at line 240 of file armreg.h.

◆ ARM11X6_AUXCTL_RA

#define ARM11X6_AUXCTL_RA   0x00000020 /* clean entire cache disable */

Definition at line 241 of file armreg.h.

◆ ARM11X6_AUXCTL_RS

#define ARM11X6_AUXCTL_RS   0x00000001 /* return stack */

Definition at line 236 of file armreg.h.

◆ ARM11X6_AUXCTL_RV

#define ARM11X6_AUXCTL_RV   0x00000040 /* block transfer cache disable */

Definition at line 242 of file armreg.h.

◆ ARM11X6_AUXCTL_SB

#define ARM11X6_AUXCTL_SB   0x00000004 /* static branch prediction */

Definition at line 238 of file armreg.h.

◆ ARM11X6_AUXCTL_TR

#define ARM11X6_AUXCTL_TR   0x00000008 /* MicroTLB replacement strat. */

Definition at line 239 of file armreg.h.

◆ ARM3_CP15_CACHEABLE

#define ARM3_CP15_CACHEABLE   3

Definition at line 141 of file armreg.h.

◆ ARM3_CP15_CONTROL

#define ARM3_CP15_CONTROL   2

Definition at line 140 of file armreg.h.

◆ ARM3_CP15_DISRUPTIVE

#define ARM3_CP15_DISRUPTIVE   5

Definition at line 143 of file armreg.h.

◆ ARM3_CP15_FLUSH

#define ARM3_CP15_FLUSH   1

Definition at line 139 of file armreg.h.

◆ ARM3_CP15_UPDATEABLE

#define ARM3_CP15_UPDATEABLE   4

Definition at line 142 of file armreg.h.

◆ ARM3_CTL_CACHE_ON

#define ARM3_CTL_CACHE_ON   0x00000001

Definition at line 146 of file armreg.h.

◆ ARM3_CTL_MONITOR

#define ARM3_CTL_MONITOR   0x00000004

Definition at line 148 of file armreg.h.

◆ ARM3_CTL_SHARED

#define ARM3_CTL_SHARED   0x00000002

Definition at line 147 of file armreg.h.

◆ ARM_A5_TLBDATA_AP

#define ARM_A5_TLBDATA_AP   __BITS(58,56)

Definition at line 585 of file armreg.h.

◆ ARM_A5_TLBDATA_ASID

#define ARM_A5_TLBDATA_ASID   __BITS(46,39)

Definition at line 593 of file armreg.h.

◆ ARM_A5_TLBDATA_B

#define ARM_A5_TLBDATA_B   __BIT(49)

Definition at line 590 of file armreg.h.

◆ ARM_A5_TLBDATA_C

#define ARM_A5_TLBDATA_C   __BIT(48)

Definition at line 591 of file armreg.h.

◆ ARM_A5_TLBDATA_DOM

#define ARM_A5_TLBDATA_DOM   __BITS(62,59)

Definition at line 584 of file armreg.h.

◆ ARM_A5_TLBDATA_nG

#define ARM_A5_TLBDATA_nG   __BIT(1)

Definition at line 601 of file armreg.h.

◆ ARM_A5_TLBDATA_NS_PAGE

#define ARM_A5_TLBDATA_NS_PAGE   __BIT(54)

Definition at line 587 of file armreg.h.

◆ ARM_A5_TLBDATA_NS_WALK

#define ARM_A5_TLBDATA_NS_WALK   __BIT(55)

Definition at line 586 of file armreg.h.

◆ ARM_A5_TLBDATA_PA

#define ARM_A5_TLBDATA_PA   __BITS(21,2)

Definition at line 600 of file armreg.h.

◆ ARM_A5_TLBDATA_S

#define ARM_A5_TLBDATA_S   __BIT(47)

Definition at line 592 of file armreg.h.

◆ ARM_A5_TLBDATA_SIZE

#define ARM_A5_TLBDATA_SIZE   __BITS(38,37)

Definition at line 594 of file armreg.h.

◆ ARM_A5_TLBDATA_SIZE_16KB

#define ARM_A5_TLBDATA_SIZE_16KB   1

Definition at line 596 of file armreg.h.

◆ ARM_A5_TLBDATA_SIZE_16MB

#define ARM_A5_TLBDATA_SIZE_16MB   3

Definition at line 598 of file armreg.h.

◆ ARM_A5_TLBDATA_SIZE_1MB

#define ARM_A5_TLBDATA_SIZE_1MB   2

Definition at line 597 of file armreg.h.

◆ ARM_A5_TLBDATA_SIZE_4KB

#define ARM_A5_TLBDATA_SIZE_4KB   0

Definition at line 595 of file armreg.h.

◆ ARM_A5_TLBDATA_TEX

#define ARM_A5_TLBDATA_TEX   __BITS(52,50)

Definition at line 589 of file armreg.h.

◆ ARM_A5_TLBDATA_VA

#define ARM_A5_TLBDATA_VA   __BITS(36,22)

Definition at line 599 of file armreg.h.

◆ ARM_A5_TLBDATA_VALID

#define ARM_A5_TLBDATA_VALID   __BIT(0)

Definition at line 602 of file armreg.h.

◆ ARM_A5_TLBDATA_XN

#define ARM_A5_TLBDATA_XN   __BIT(53)

Definition at line 588 of file armreg.h.

◆ ARM_A5_TLBDATAOP_INDEX

#define ARM_A5_TLBDATAOP_INDEX   __BITS(5,0)

Definition at line 659 of file armreg.h.

◆ ARM_A7_TLBDATA01_ASID

#define ARM_A7_TLBDATA01_ASID   __BITS(33,26)

Definition at line 641 of file armreg.h.

◆ ARM_A7_TLBDATA0_NS_WALK

#define ARM_A7_TLBDATA0_NS_WALK   __BIT(4)

Definition at line 645 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE

#define ARM_A7_TLBDATA0_SIZE   __BITS(3,1)

Definition at line 646 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_LPAE_1GB

#define ARM_A7_TLBDATA0_SIZE_LPAE_1GB   7

Definition at line 654 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_LPAE_2MB

#define ARM_A7_TLBDATA0_SIZE_LPAE_2MB   5

Definition at line 652 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_LPAE_4KB

#define ARM_A7_TLBDATA0_SIZE_LPAE_4KB   1

Definition at line 648 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_LPAE_64KB

#define ARM_A7_TLBDATA0_SIZE_LPAE_64KB   3

Definition at line 650 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_V7_16MB

#define ARM_A7_TLBDATA0_SIZE_V7_16MB   6

Definition at line 653 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_V7_1MB

#define ARM_A7_TLBDATA0_SIZE_V7_1MB   4

Definition at line 651 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_V7_4KB

#define ARM_A7_TLBDATA0_SIZE_V7_4KB   0

Definition at line 647 of file armreg.h.

◆ ARM_A7_TLBDATA0_SIZE_V7_64KB

#define ARM_A7_TLBDATA0_SIZE_V7_64KB   2

Definition at line 649 of file armreg.h.

◆ ARM_A7_TLBDATA0_VA

#define ARM_A7_TLBDATA0_VA   __BITS(17,5)

Definition at line 644 of file armreg.h.

◆ ARM_A7_TLBDATA0_VMID

#define ARM_A7_TLBDATA0_VMID   __BITS(25,18)

Definition at line 643 of file armreg.h.

◆ ARM_A7_TLBDATA12_PA

#define ARM_A7_TLBDATA12_PA   __BITS(68-32,41-32)

Definition at line 634 of file armreg.h.

◆ ARM_A7_TLBDATA1_AP

#define ARM_A7_TLBDATA1_AP   __BITS(37-32,35-32)

Definition at line 638 of file armreg.h.

◆ ARM_A7_TLBDATA1_HAP

#define ARM_A7_TLBDATA1_HAP   __BITS(39-32,38-32)

Definition at line 637 of file armreg.h.

◆ ARM_A7_TLBDATA1_nG

#define ARM_A7_TLBDATA1_nG   __BIT(34-32)

Definition at line 639 of file armreg.h.

◆ ARM_A7_TLBDATA1_NS

#define ARM_A7_TLBDATA1_NS   __BIT(40-32)

Definition at line 636 of file armreg.h.

◆ ARM_A7_TLBDATA2_DOM

#define ARM_A7_TLBDATA2_DOM   __BITS(81-64,78-64)

Definition at line 610 of file armreg.h.

◆ ARM_A7_TLBDATA2_IS

#define ARM_A7_TLBDATA2_IS   __BITS(77-64,76-64)

Definition at line 611 of file armreg.h.

◆ ARM_A7_TLBDATA2_IS_DSO

#define ARM_A7_TLBDATA2_IS_DSO   3

Definition at line 615 of file armreg.h.

◆ ARM_A7_TLBDATA2_IS_NC

#define ARM_A7_TLBDATA2_IS_NC   0

Definition at line 612 of file armreg.h.

◆ ARM_A7_TLBDATA2_IS_WB_WA

#define ARM_A7_TLBDATA2_IS_WB_WA   1

Definition at line 613 of file armreg.h.

◆ ARM_A7_TLBDATA2_IS_WT

#define ARM_A7_TLBDATA2_IS_WT   2

Definition at line 614 of file armreg.h.

◆ ARM_A7_TLBDATA2_OS

#define ARM_A7_TLBDATA2_OS   __BITS(75-64,74-64)

Definition at line 620 of file armreg.h.

◆ ARM_A7_TLBDATA2_OS_NC

#define ARM_A7_TLBDATA2_OS_NC   0

Definition at line 621 of file armreg.h.

◆ ARM_A7_TLBDATA2_OS_WB

#define ARM_A7_TLBDATA2_OS_WB   3

Definition at line 624 of file armreg.h.

◆ ARM_A7_TLBDATA2_OS_WB_WA

#define ARM_A7_TLBDATA2_OS_WB_WA   1

Definition at line 622 of file armreg.h.

◆ ARM_A7_TLBDATA2_OS_WT

#define ARM_A7_TLBDATA2_OS_WT   2

Definition at line 623 of file armreg.h.

◆ ARM_A7_TLBDATA2_PXN

#define ARM_A7_TLBDATA2_PXN   __BIT(69-64)

Definition at line 632 of file armreg.h.

◆ ARM_A7_TLBDATA2_S1_SIZE

#define ARM_A7_TLBDATA2_S1_SIZE   __BITS(83-64,82-64)

Definition at line 605 of file armreg.h.

◆ ARM_A7_TLBDATA2_S1_SIZE_16MB

#define ARM_A7_TLBDATA2_S1_SIZE_16MB   3

Definition at line 609 of file armreg.h.

◆ ARM_A7_TLBDATA2_S1_SIZE_1MB

#define ARM_A7_TLBDATA2_S1_SIZE_1MB   2

Definition at line 608 of file armreg.h.

◆ ARM_A7_TLBDATA2_S1_SIZE_4KB

#define ARM_A7_TLBDATA2_S1_SIZE_4KB   0

Definition at line 606 of file armreg.h.

◆ ARM_A7_TLBDATA2_S1_SIZE_64KB

#define ARM_A7_TLBDATA2_S1_SIZE_64KB   1

Definition at line 607 of file armreg.h.

◆ ARM_A7_TLBDATA2_S2_LEVEL

#define ARM_A7_TLBDATA2_S2_LEVEL   __BITS(85-64,84-64)

Definition at line 604 of file armreg.h.

◆ ARM_A7_TLBDATA2_S2OVR

#define ARM_A7_TLBDATA2_S2OVR   __BIT(75-64)

Definition at line 616 of file armreg.h.

◆ ARM_A7_TLBDATA2_SDO_MT

#define ARM_A7_TLBDATA2_SDO_MT   __BITS(74-64,72-64)

Definition at line 617 of file armreg.h.

◆ ARM_A7_TLBDATA2_SDO_MT_D

#define ARM_A7_TLBDATA2_SDO_MT_D   2

Definition at line 618 of file armreg.h.

◆ ARM_A7_TLBDATA2_SDO_MT_SO

#define ARM_A7_TLBDATA2_SDO_MT_SO   6

Definition at line 619 of file armreg.h.

◆ ARM_A7_TLBDATA2_SH

#define ARM_A7_TLBDATA2_SH   __BITS(73-64,72-64)

Definition at line 625 of file armreg.h.

◆ ARM_A7_TLBDATA2_SH_IS

#define ARM_A7_TLBDATA2_SH_IS   3

Definition at line 629 of file armreg.h.

◆ ARM_A7_TLBDATA2_SH_NONE

#define ARM_A7_TLBDATA2_SH_NONE   0

Definition at line 626 of file armreg.h.

◆ ARM_A7_TLBDATA2_SH_OS

#define ARM_A7_TLBDATA2_SH_OS   2

Definition at line 628 of file armreg.h.

◆ ARM_A7_TLBDATA2_SH_UNUSED

#define ARM_A7_TLBDATA2_SH_UNUSED   1

Definition at line 627 of file armreg.h.

◆ ARM_A7_TLBDATA2_XN1

#define ARM_A7_TLBDATA2_XN1   __BIT(70-64)

Definition at line 631 of file armreg.h.

◆ ARM_A7_TLBDATA2_XN2

#define ARM_A7_TLBDATA2_XN2   __BIT(71-64)

Definition at line 630 of file armreg.h.

◆ ARM_A7_TLBDATAOP_INDEX

#define ARM_A7_TLBDATAOP_INDEX   __BITS(6,0)

Definition at line 660 of file armreg.h.

◆ ARM_CP15_CPU_ID

#define ARM_CP15_CPU_ID   0

Definition at line 107 of file armreg.h.

◆ ARM_ISA3_SYNCHPRIM_LDREX

#define ARM_ISA3_SYNCHPRIM_LDREX   0x10

Definition at line 112 of file armreg.h.

◆ ARM_ISA3_SYNCHPRIM_LDREXD

#define ARM_ISA3_SYNCHPRIM_LDREXD   0x20

Definition at line 114 of file armreg.h.

◆ ARM_ISA3_SYNCHPRIM_LDREXPLUS

#define ARM_ISA3_SYNCHPRIM_LDREXPLUS   0x13

Definition at line 113 of file armreg.h.

◆ ARM_ISA3_SYNCHPRIM_MASK

#define ARM_ISA3_SYNCHPRIM_MASK   0x0000f000

Definition at line 110 of file armreg.h.

◆ ARM_ISA4_SYNCHPRIM_MASK

#define ARM_ISA4_SYNCHPRIM_MASK   0x00f00000

Definition at line 111 of file armreg.h.

◆ ARM_MVFR0_ASIMD_MASK

#define ARM_MVFR0_ASIMD_MASK   0x0000000f

Definition at line 128 of file armreg.h.

◆ ARM_MVFR0_DFLOAT_MASK

#define ARM_MVFR0_DFLOAT_MASK   0x00000f00

Definition at line 126 of file armreg.h.

◆ ARM_MVFR0_DIVIDE_MASK

#define ARM_MVFR0_DIVIDE_MASK   0x000f0000

Definition at line 124 of file armreg.h.

◆ ARM_MVFR0_EXCEPT_MASK

#define ARM_MVFR0_EXCEPT_MASK   0x0000f000

Definition at line 125 of file armreg.h.

◆ ARM_MVFR0_ROUNDING_MASK

#define ARM_MVFR0_ROUNDING_MASK   0xf0000000

Definition at line 121 of file armreg.h.

◆ ARM_MVFR0_SFLOAT_MASK

#define ARM_MVFR0_SFLOAT_MASK   0x000000f0

Definition at line 127 of file armreg.h.

◆ ARM_MVFR0_SHORTVEC_MASK

#define ARM_MVFR0_SHORTVEC_MASK   0x0f000000

Definition at line 122 of file armreg.h.

◆ ARM_MVFR0_SQRT_MASK

#define ARM_MVFR0_SQRT_MASK   0x00f00000

Definition at line 123 of file armreg.h.

◆ ARM_MVFR1_ASIMD_FMACS_MASK

#define ARM_MVFR1_ASIMD_FMACS_MASK   0xf0000000

Definition at line 129 of file armreg.h.

◆ ARM_MVFR1_ASIMD_HPFP_MASK

#define ARM_MVFR1_ASIMD_HPFP_MASK   0x00f00000

Definition at line 131 of file armreg.h.

◆ ARM_MVFR1_ASIMD_INT_MASK

#define ARM_MVFR1_ASIMD_INT_MASK   0x0000f000

Definition at line 133 of file armreg.h.

◆ ARM_MVFR1_ASIMD_LDST_MASK

#define ARM_MVFR1_ASIMD_LDST_MASK   0x00000f00

Definition at line 134 of file armreg.h.

◆ ARM_MVFR1_ASIMD_SPFP_MASK

#define ARM_MVFR1_ASIMD_SPFP_MASK   0x000f0000

Definition at line 132 of file armreg.h.

◆ ARM_MVFR1_D_NAN_MASK

#define ARM_MVFR1_D_NAN_MASK   0x000000f0

Definition at line 135 of file armreg.h.

◆ ARM_MVFR1_FTZ_MASK

#define ARM_MVFR1_FTZ_MASK   0x0000000f

Definition at line 136 of file armreg.h.

◆ ARM_MVFR1_VFP_HPFP_MASK

#define ARM_MVFR1_VFP_HPFP_MASK   0x0f000000

Definition at line 130 of file armreg.h.

◆ ARM_PFR0_THUMBEE_MASK

#define ARM_PFR0_THUMBEE_MASK   0x0000f000

Definition at line 115 of file armreg.h.

◆ ARM_PFR1_GTIMER_MASK

#define ARM_PFR1_GTIMER_MASK   0x000f0000

Definition at line 116 of file armreg.h.

◆ ARM_PFR1_SEC_MASK

#define ARM_PFR1_SEC_MASK   0x000000f0

Definition at line 118 of file armreg.h.

◆ ARM_PFR1_VIRT_MASK

#define ARM_PFR1_VIRT_MASK   0x0000f000

Definition at line 117 of file armreg.h.

◆ ARM_TLBDATA_VALID

#define ARM_TLBDATA_VALID   __BIT(0)

Definition at line 656 of file armreg.h.

◆ ARM_TLBDATAOP_WAY

#define ARM_TLBDATAOP_WAY   __BIT(31)

Definition at line 658 of file armreg.h.

◆ ARM_VECTORS_HIGH

#define ARM_VECTORS_HIGH   0xffff0000U

Definition at line 404 of file armreg.h.

◆ ARM_VECTORS_LOW

#define ARM_VECTORS_LOW   0x00000000U

Definition at line 403 of file armreg.h.

◆ ARMREG_READ64_INLINE

#define ARMREG_READ64_INLINE (   name,
  __insnstring 
)
Value:
static inline uint64_t armreg_##name##_read(void) \
{ \
uint64_t __rv; \
__asm __volatile("mrrc " __insnstring : "=r"(__rv)); \
return __rv; \
}

Definition at line 734 of file armreg.h.

◆ ARMREG_READ_INLINE

#define ARMREG_READ_INLINE (   name,
  __insnstring 
)
Value:
static inline uint32_t armreg_##name##_read(void) \
{ \
uint32_t __rv; \
__asm __volatile("mrc " __insnstring : "=r"(__rv)); \
return __rv; \
}

Definition at line 704 of file armreg.h.

◆ ARMREG_READ_INLINE2

#define ARMREG_READ_INLINE2 (   name,
  __insnstring 
)
Value:
static inline uint32_t armreg_##name##_read(void) \
{ \
uint32_t __rv; \
__asm __volatile(".fpu vfp"); \
__asm __volatile(__insnstring : "=r"(__rv)); \
return __rv; \
}

Definition at line 718 of file armreg.h.

◆ ARMREG_WRITE64_INLINE

#define ARMREG_WRITE64_INLINE (   name,
  __insnstring 
)
Value:
static inline void armreg_##name##_write(uint64_t __val) \
{ \
__asm __volatile("mcrr " __insnstring :: "r"(__val)); \
}

Definition at line 742 of file armreg.h.

◆ ARMREG_WRITE_INLINE

#define ARMREG_WRITE_INLINE (   name,
  __insnstring 
)
Value:
static inline void armreg_##name##_write(uint32_t __val) \
{ \
__asm __volatile("mcr " __insnstring :: "r"(__val)); \
}

Definition at line 712 of file armreg.h.

◆ ARMREG_WRITE_INLINE2

#define ARMREG_WRITE_INLINE2 (   name,
  __insnstring 
)
Value:
static inline void armreg_##name##_write(uint32_t __val) \
{ \
__asm __volatile(".fpu vfp"); \
__asm __volatile(__insnstring :: "r"(__val)); \
}

Definition at line 727 of file armreg.h.

◆ CNTCTL_ENABLE

#define CNTCTL_ENABLE   __BIT(0)

Definition at line 567 of file armreg.h.

◆ CNTCTL_IMASK

#define CNTCTL_IMASK   __BIT(1)

Definition at line 566 of file armreg.h.

◆ CNTCTL_ISTATUS

#define CNTCTL_ISTATUS   __BIT(2)

Definition at line 565 of file armreg.h.

◆ CNTHCTL_EVNTDIR

#define CNTHCTL_EVNTDIR   __BIT(3)

Definition at line 579 of file armreg.h.

◆ CNTHCTL_EVNTEN

#define CNTHCTL_EVNTEN   __BIT(2)

Definition at line 580 of file armreg.h.

◆ CNTHCTL_EVNTI

#define CNTHCTL_EVNTI   __BITS(7,4)

Definition at line 578 of file armreg.h.

◆ CNTHCTL_PL1PCEN

#define CNTHCTL_PL1PCEN   __BIT(1)

Definition at line 581 of file armreg.h.

◆ CNTHCTL_PL1PCTEN

#define CNTHCTL_PL1PCTEN   __BIT(0)

Definition at line 582 of file armreg.h.

◆ CNTKCTL_EVNTDIR

#define CNTKCTL_EVNTDIR   __BIT(3) /* CNTVCT Event Dir (1->0) */

Definition at line 572 of file armreg.h.

◆ CNTKCTL_EVNTEN

#define CNTKCTL_EVNTEN   __BIT(2) /* CNTVCT Event Enable */

Definition at line 573 of file armreg.h.

◆ CNTKCTL_EVNTI

#define CNTKCTL_EVNTI   __BITS(7,4) /* CNTVCT Event Bit Select */

Definition at line 571 of file armreg.h.

◆ CNTKCTL_PL0PCTEN

#define CNTKCTL_PL0PCTEN   __BIT(0) /* PL0 Physical Counter Enable */

Definition at line 575 of file armreg.h.

◆ CNTKCTL_PL0PTEN

#define CNTKCTL_PL0PTEN   __BIT(9) /* PL0 Physical Timer Enable */

Definition at line 569 of file armreg.h.

◆ CNTKCTL_PL0VCTEN

#define CNTKCTL_PL0VCTEN   __BIT(1) /* PL0 Virtual Counter Enable */

Definition at line 574 of file armreg.h.

◆ CNTKCTL_PL0VTEN

#define CNTKCTL_PL0VTEN   __BIT(8) /* PL0 Virtual Timer Enable */

Definition at line 570 of file armreg.h.

◆ CORTEX_CNTENC_C

#define CORTEX_CNTENC_C   __BIT(31) /* Disables the cycle counter */

Definition at line 485 of file armreg.h.

◆ CORTEX_CNTENS_C

#define CORTEX_CNTENS_C   __BIT(31) /* Enables the cycle counter */

Definition at line 484 of file armreg.h.

◆ CORTEX_CNTOFL_C

#define CORTEX_CNTOFL_C   __BIT(31) /* Cycle counter overflow flag */

Definition at line 486 of file armreg.h.

◆ CORTEXA15_ACTLR_BTB

#define CORTEXA15_ACTLR_BTB   __BIT(0) /* Cache and TLB updates broadcast */

Definition at line 311 of file armreg.h.

◆ CORTEXA15_ACTLR_IOBEU

#define CORTEXA15_ACTLR_IOBEU   __BIT(15) /* In order issue in Branch Exec Unit */

Definition at line 313 of file armreg.h.

◆ CORTEXA15_ACTLR_SDEH

#define CORTEXA15_ACTLR_SDEH   __BIT(31) /* snoop-delayed exclusive handling */

Definition at line 314 of file armreg.h.

◆ CORTEXA15_ACTLR_SMP

#define CORTEXA15_ACTLR_SMP   __BIT(6) /* SMP */

Definition at line 312 of file armreg.h.

◆ CORTEXA5_ACTLR_EXCL

#define CORTEXA5_ACTLR_EXCL   __BIT(7) /* Exclusive L1/L2 cache control */

Definition at line 289 of file armreg.h.

◆ CORTEXA5_ACTLR_FW

#define CORTEXA5_ACTLR_FW   __BIT(0)

Definition at line 287 of file armreg.h.

◆ CORTEXA5_ACTLR_SMP

#define CORTEXA5_ACTLR_SMP   __BIT(6) /* Inner Cache Shared is cacheable */

Definition at line 288 of file armreg.h.

◆ CORTEXA7_ACTLR_L1ALIAS

#define CORTEXA7_ACTLR_L1ALIAS   __BIT(0) /* Enables L1 cache alias checks */

Definition at line 292 of file armreg.h.

◆ CORTEXA7_ACTLR_L2EN

#define CORTEXA7_ACTLR_L2EN   __BIT(1) /* Enables L2 cache */

Definition at line 293 of file armreg.h.

◆ CORTEXA7_ACTLR_SMP

#define CORTEXA7_ACTLR_SMP   __BIT(6) /* SMP */

Definition at line 294 of file armreg.h.

◆ CORTEXA8_ACTLR_L1ALIAS

#define CORTEXA8_ACTLR_L1ALIAS   __BIT(0) /* Enables L1 cache alias checks */

Definition at line 297 of file armreg.h.

◆ CORTEXA8_ACTLR_L2EN

#define CORTEXA8_ACTLR_L2EN   __BIT(1) /* Enables L2 cache */

Definition at line 298 of file armreg.h.

◆ CORTEXA9_AUXCTL_EXCL

#define CORTEXA9_AUXCTL_EXCL   0x00000080 /* Exclusive cache bit */

Definition at line 306 of file armreg.h.

◆ CORTEXA9_AUXCTL_FW

#define CORTEXA9_AUXCTL_FW   0x00000001 /* Cache and TLB updates broadcast */

Definition at line 301 of file armreg.h.

◆ CORTEXA9_AUXCTL_L1PE

#define CORTEXA9_AUXCTL_L1PE   0x00000004 /* Data prefetch hint enable */

Definition at line 303 of file armreg.h.

◆ CORTEXA9_AUXCTL_L2PE

#define CORTEXA9_AUXCTL_L2PE   0x00000002 /* Prefetch hint enable */

Definition at line 302 of file armreg.h.

◆ CORTEXA9_AUXCTL_ONEWAY

#define CORTEXA9_AUXCTL_ONEWAY   0x00000100 /* Allocate in on cache way only */

Definition at line 307 of file armreg.h.

◆ CORTEXA9_AUXCTL_PARITY

#define CORTEXA9_AUXCTL_PARITY   0x00000200 /* Support parity checking */

Definition at line 308 of file armreg.h.

◆ CORTEXA9_AUXCTL_SMP

#define CORTEXA9_AUXCTL_SMP   0x00000040 /* Coherency is active */

Definition at line 305 of file armreg.h.

◆ CORTEXA9_AUXCTL_WR_ZERO

#define CORTEXA9_AUXCTL_WR_ZERO   0x00000008 /* Ena. write full line of 0s mode */

Definition at line 304 of file armreg.h.

◆ CORTEXA9_MPIDR_CLID

#define CORTEXA9_MPIDR_CLID   __BITS(11,8) /* AFF1 = cluster id */

Definition at line 554 of file armreg.h.

◆ CORTEXA9_MPIDR_CPUID

#define CORTEXA9_MPIDR_CPUID   __BITS(0,1) /* AFF0 = physical core id */

Definition at line 555 of file armreg.h.

◆ CORTEXA9_MPIDR_MP

#define CORTEXA9_MPIDR_MP   MPIDR_MP

Definition at line 552 of file armreg.h.

◆ CORTEXA9_MPIDR_U

#define CORTEXA9_MPIDR_U   MPIDR_U

Definition at line 553 of file armreg.h.

◆ CPACR_ALL

#define CPACR_ALL   3 /* Privileged and User mode access */

Definition at line 226 of file armreg.h.

◆ CPACR_CPn

#define CPACR_CPn (   n)    (3 << (2*n))

Definition at line 222 of file armreg.h.

◆ CPACR_NOACCESS

#define CPACR_NOACCESS   0 /* reset value */

Definition at line 223 of file armreg.h.

◆ CPACR_PRIVED

#define CPACR_PRIVED   1 /* Privileged mode access */

Definition at line 224 of file armreg.h.

◆ CPACR_RESERVED

#define CPACR_RESERVED   2

Definition at line 225 of file armreg.h.

◆ CPACR_V7_ASEDIS

#define CPACR_V7_ASEDIS   0x80000000 /* Disable Advanced SIMD Ext. */

Definition at line 220 of file armreg.h.

◆ CPACR_V7_D32DIS

#define CPACR_V7_D32DIS   0x40000000 /* Disable VFP regs 15-31 */

Definition at line 221 of file armreg.h.

◆ CPU_CONTROL_32BD_ENABLE

#define CPU_CONTROL_32BD_ENABLE   0x00000020 /* D: 32-bit addressing */

Definition at line 192 of file armreg.h.

◆ CPU_CONTROL_32BP_ENABLE

#define CPU_CONTROL_32BP_ENABLE   0x00000010 /* P: 32-bit exception handlers */

Definition at line 191 of file armreg.h.

◆ CPU_CONTROL_AF_ENABLE

#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */

Definition at line 214 of file armreg.h.

◆ CPU_CONTROL_AFLT_ENABLE

#define CPU_CONTROL_AFLT_ENABLE   0x00000002 /* A: Alignment fault enable */

Definition at line 188 of file armreg.h.

◆ CPU_CONTROL_BEND_ENABLE

#define CPU_CONTROL_BEND_ENABLE   0x00000080 /* B: Big-endian mode */

Definition at line 194 of file armreg.h.

◆ CPU_CONTROL_BPRD_ENABLE

#define CPU_CONTROL_BPRD_ENABLE   0x00000800 /* Z: Branch prediction enable */

Definition at line 199 of file armreg.h.

◆ CPU_CONTROL_CPCLK

#define CPU_CONTROL_CPCLK   0x00000400 /* F: Implementation defined */

Definition at line 197 of file armreg.h.

◆ CPU_CONTROL_DC_ENABLE

#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */

Definition at line 189 of file armreg.h.

◆ CPU_CONTROL_EX_BEND

#define CPU_CONTROL_EX_BEND   0x02000000 /* EE: exception endianness */

Definition at line 211 of file armreg.h.

◆ CPU_CONTROL_FI_ENABLE

#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */

Definition at line 207 of file armreg.h.

◆ CPU_CONTROL_HA_ENABLE

#define CPU_CONTROL_HA_ENABLE   0x00020000 /* HA: Hardware Access flag enable */

Definition at line 204 of file armreg.h.

◆ CPU_CONTROL_IC_ENABLE

#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */

Definition at line 200 of file armreg.h.

◆ CPU_CONTROL_IDC_ENABLE

#define CPU_CONTROL_IDC_ENABLE   CPU_CONTROL_DC_ENABLE

Definition at line 217 of file armreg.h.

◆ CPU_CONTROL_LABT_ENABLE

#define CPU_CONTROL_LABT_ENABLE   0x00000040 /* L: Late abort enable */

Definition at line 193 of file armreg.h.

◆ CPU_CONTROL_MMU_ENABLE

#define CPU_CONTROL_MMU_ENABLE   0x00000001 /* M: MMU/Protection unit enable */

Definition at line 187 of file armreg.h.

◆ CPU_CONTROL_NMFI

#define CPU_CONTROL_NMFI   0x08000000 /* NMFI: Non maskable FIQ */

Definition at line 212 of file armreg.h.

◆ CPU_CONTROL_ROM_ENABLE

#define CPU_CONTROL_ROM_ENABLE   0x00000200 /* R: ROM protection bit */

Definition at line 196 of file armreg.h.

◆ CPU_CONTROL_ROUNDROBIN

#define CPU_CONTROL_ROUNDROBIN   0x00004000 /* RR: Predictable replacement */

Definition at line 202 of file armreg.h.

◆ CPU_CONTROL_SWP_ENABLE

#define CPU_CONTROL_SWP_ENABLE   0x00000400 /* SW: SWP{B} perform normally. */

Definition at line 198 of file armreg.h.

◆ CPU_CONTROL_SYST_ENABLE

#define CPU_CONTROL_SYST_ENABLE   0x00000100 /* S: System protection bit */

Definition at line 195 of file armreg.h.

◆ CPU_CONTROL_TE_ENABLE

#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */

Definition at line 215 of file armreg.h.

◆ CPU_CONTROL_TR_ENABLE

#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */

Definition at line 213 of file armreg.h.

◆ CPU_CONTROL_UNAL_ENABLE

#define CPU_CONTROL_UNAL_ENABLE   0x00400000 /* U: unaligned data access */

Definition at line 208 of file armreg.h.

◆ CPU_CONTROL_UWXN_ENABLE

#define CPU_CONTROL_UWXN_ENABLE   0x00100000 /* UWXN: User Write eXecute Never */

Definition at line 206 of file armreg.h.

◆ CPU_CONTROL_V4COMPAT

#define CPU_CONTROL_V4COMPAT   0x00008000 /* L4: ARMv4 compat LDR R15 etc */

Definition at line 203 of file armreg.h.

◆ CPU_CONTROL_V_ENABLE

#define CPU_CONTROL_V_ENABLE   0x01000000 /* VE: Interrupt vectors enable */

Definition at line 210 of file armreg.h.

◆ CPU_CONTROL_VECRELOC

#define CPU_CONTROL_VECRELOC   0x00002000 /* V: Vector relocation */

Definition at line 201 of file armreg.h.

◆ CPU_CONTROL_WBUF_ENABLE

#define CPU_CONTROL_WBUF_ENABLE   0x00000008 /* W: Write buffer enable */

Definition at line 190 of file armreg.h.

◆ CPU_CONTROL_WXN_ENABLE

#define CPU_CONTROL_WXN_ENABLE   0x00080000 /* WXN: Write Execute Never */

Definition at line 205 of file armreg.h.

◆ CPU_CONTROL_XP_ENABLE

#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */

Definition at line 209 of file armreg.h.

◆ CPU_CSID_ASSOC

#define CPU_CSID_ASSOC (   x)    (((x) >> 3) & 0x1ff)

Definition at line 364 of file armreg.h.

◆ CPU_CSID_CTYPE_RA

#define CPU_CSID_CTYPE_RA   0x20000000 /* read-allocation avail */

Definition at line 361 of file armreg.h.

◆ CPU_CSID_CTYPE_WA

#define CPU_CSID_CTYPE_WA   0x10000000 /* write-allocation avail */

Definition at line 362 of file armreg.h.

◆ CPU_CSID_CTYPE_WB

#define CPU_CSID_CTYPE_WB   0x40000000 /* write-back avail */

Definition at line 360 of file armreg.h.

◆ CPU_CSID_CTYPE_WT

#define CPU_CSID_CTYPE_WT   0x80000000 /* write-through avail */

Definition at line 359 of file armreg.h.

◆ CPU_CSID_LEN

#define CPU_CSID_LEN (   x)    ((x) & 0x07)

Definition at line 365 of file armreg.h.

◆ CPU_CSID_NUMSETS

#define CPU_CSID_NUMSETS (   x)    (((x) >> 13) & 0x7fff)

Definition at line 363 of file armreg.h.

◆ CPU_CSSR_InD

#define CPU_CSSR_InD   0x00000001

Definition at line 370 of file armreg.h.

◆ CPU_CSSR_L1

#define CPU_CSSR_L1   0x00000000

Definition at line 369 of file armreg.h.

◆ CPU_CSSR_L2

#define CPU_CSSR_L2   0x00000002

Definition at line 368 of file armreg.h.

◆ CPU_CT4_CWG

#define CPU_CT4_CWG (   x)    (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */

Definition at line 356 of file armreg.h.

◆ CPU_CT4_DLINE

#define CPU_CT4_DLINE (   x)    (((x) >> 16) & 0xf) /* D$ line size */

Definition at line 350 of file armreg.h.

◆ CPU_CT4_ERG

#define CPU_CT4_ERG (   x)    (((x) >> 20) & 0xf) /* Cache WriteBack Granule */

Definition at line 355 of file armreg.h.

◆ CPU_CT4_ILINE

#define CPU_CT4_ILINE (   x)    ((x) & 0xf) /* I$ line size */

Definition at line 349 of file armreg.h.

◆ CPU_CT4_L1_AIVIVT

#define CPU_CT4_L1_AIVIVT   1 /* ASID tagged VIVT */

Definition at line 352 of file armreg.h.

◆ CPU_CT4_L1_PIPT

#define CPU_CT4_L1_PIPT   3 /* PIPT */

Definition at line 354 of file armreg.h.

◆ CPU_CT4_L1_VIPT

#define CPU_CT4_L1_VIPT   2 /* VIPT */

Definition at line 353 of file armreg.h.

◆ CPU_CT4_L1IPOLICY

#define CPU_CT4_L1IPOLICY (   x)    (((x) >> 14) & 0x3) /* I$ policy */

Definition at line 351 of file armreg.h.

◆ CPU_CT_CTYPE

#define CPU_CT_CTYPE (   x)    (((x) >> 25) & 0xf) /* cache type */

Definition at line 333 of file armreg.h.

◆ CPU_CT_CTYPE_WB1

#define CPU_CT_CTYPE_WB1   1 /* write-back, clean w/ read */

Definition at line 336 of file armreg.h.

◆ CPU_CT_CTYPE_WB14

#define CPU_CT_CTYPE_WB14   14 /* w/b, cp15,7, lockdown fmt C */

Definition at line 340 of file armreg.h.

◆ CPU_CT_CTYPE_WB2

#define CPU_CT_CTYPE_WB2   2 /* w/b, clean w/ cp15,7 */

Definition at line 337 of file armreg.h.

◆ CPU_CT_CTYPE_WB6

#define CPU_CT_CTYPE_WB6   6 /* w/b, cp15,7, lockdown fmt A */

Definition at line 338 of file armreg.h.

◆ CPU_CT_CTYPE_WB7

#define CPU_CT_CTYPE_WB7   7 /* w/b, cp15,7, lockdown fmt B */

Definition at line 339 of file armreg.h.

◆ CPU_CT_CTYPE_WT

#define CPU_CT_CTYPE_WT   0 /* write-through */

Definition at line 335 of file armreg.h.

◆ CPU_CT_DSIZE

#define CPU_CT_DSIZE (   x)    (((x) >> 12) & 0xfff) /* D$ info */

Definition at line 331 of file armreg.h.

◆ CPU_CT_FORMAT

#define CPU_CT_FORMAT (   x)    (((x) >> 29) & 0x7) /* reg format */

Definition at line 329 of file armreg.h.

◆ CPU_CT_ISIZE

#define CPU_CT_ISIZE (   x)    ((x) & 0xfff) /* I$ info */

Definition at line 330 of file armreg.h.

◆ CPU_CT_S

#define CPU_CT_S   (1U << 24) /* split cache */

Definition at line 332 of file armreg.h.

◆ CPU_CT_xSIZE_ASSOC

#define CPU_CT_xSIZE_ASSOC (   x)    (((x) >> 3) & 0x7) /* associativity */

Definition at line 344 of file armreg.h.

◆ CPU_CT_xSIZE_LEN

#define CPU_CT_xSIZE_LEN (   x)    ((x) & 0x3) /* line size */

Definition at line 342 of file armreg.h.

◆ CPU_CT_xSIZE_M

#define CPU_CT_xSIZE_M   (1U << 2) /* multiplier */

Definition at line 343 of file armreg.h.

◆ CPU_CT_xSIZE_P

#define CPU_CT_xSIZE_P   (1U << 11) /* need to page-color */

Definition at line 346 of file armreg.h.

◆ CPU_CT_xSIZE_SIZE

#define CPU_CT_xSIZE_SIZE (   x)    (((x) >> 6) & 0x7) /* size */

Definition at line 345 of file armreg.h.

◆ F32_bit

#define F32_bit   (1 << 6) /* FIQ disable */

Definition at line 80 of file armreg.h.

◆ FAULT_ALIGN_0

#define FAULT_ALIGN_0   0x01 /* Alignment */

Definition at line 385 of file armreg.h.

◆ FAULT_ALIGN_1

#define FAULT_ALIGN_1   0x03 /* Alignment */

Definition at line 386 of file armreg.h.

◆ FAULT_BUSERR_0

#define FAULT_BUSERR_0   0x04 /* External Abort on Linefetch -- Section */

Definition at line 379 of file armreg.h.

◆ FAULT_BUSERR_1

#define FAULT_BUSERR_1   0x06 /* External Abort on Linefetch -- Page */

Definition at line 380 of file armreg.h.

◆ FAULT_BUSERR_2

#define FAULT_BUSERR_2   0x08 /* External Abort on Non-linefetch -- Section */

Definition at line 381 of file armreg.h.

◆ FAULT_BUSERR_3

#define FAULT_BUSERR_3   0x0a /* External Abort on Non-linefetch -- Page */

Definition at line 382 of file armreg.h.

◆ FAULT_BUSTRNL1

#define FAULT_BUSTRNL1   0x0c /* External abort on Translation -- Level 1 */

Definition at line 383 of file armreg.h.

◆ FAULT_BUSTRNL2

#define FAULT_BUSTRNL2   0x0e /* External abort on Translation -- Level 2 */

Definition at line 384 of file armreg.h.

◆ FAULT_CM

#define FAULT_CM   0x2000 /* fault was due to cache maintenance (ARMv7+) */

Definition at line 398 of file armreg.h.

◆ FAULT_DOMAIN_P

#define FAULT_DOMAIN_P   0x0b /* Domain -- Page */

Definition at line 390 of file armreg.h.

◆ FAULT_DOMAIN_S

#define FAULT_DOMAIN_S   0x09 /* Domain -- Section */

Definition at line 389 of file armreg.h.

◆ FAULT_EXT

#define FAULT_EXT   0x1000 /* fault was due to external abort (ARMv6+) */

Definition at line 397 of file armreg.h.

◆ FAULT_IMPRECISE

#define FAULT_IMPRECISE   0x0400 /* Imprecise exception (XSCALE) */

Definition at line 395 of file armreg.h.

◆ FAULT_LPAE

#define FAULT_LPAE   0x0200 /* (SW) used long descriptors */

Definition at line 394 of file armreg.h.

◆ FAULT_PERM_P

#define FAULT_PERM_P   0x0f /* Permission -- Page */

Definition at line 392 of file armreg.h.

◆ FAULT_PERM_S

#define FAULT_PERM_S   0x0d /* Permission -- Section */

Definition at line 391 of file armreg.h.

◆ FAULT_TRANS_P

#define FAULT_TRANS_P   0x07 /* Translation -- Page */

Definition at line 388 of file armreg.h.

◆ FAULT_TRANS_S

#define FAULT_TRANS_S   0x05 /* Translation -- Section */

Definition at line 387 of file armreg.h.

◆ FAULT_TYPE_MASK

#define FAULT_TYPE_MASK   0x0f

Definition at line 374 of file armreg.h.

◆ FAULT_USER

#define FAULT_USER   0x10

Definition at line 375 of file armreg.h.

◆ FAULT_WRITE

#define FAULT_WRITE   0x0800 /* fault was due to write (ARMv6+) */

Definition at line 396 of file armreg.h.

◆ FAULT_WRTBUF_0

#define FAULT_WRTBUF_0   0x00 /* Vector Exception */

Definition at line 377 of file armreg.h.

◆ FAULT_WRTBUF_1

#define FAULT_WRTBUF_1   0x02 /* Terminal Exception */

Definition at line 378 of file armreg.h.

◆ FC_BRANCH_TARG_BUF_DIS

#define FC_BRANCH_TARG_BUF_DIS   0x00020000 /* Branch Target Buffer Disable */

Definition at line 325 of file armreg.h.

◆ FC_DCACHE_REPL_LOCK

#define FC_DCACHE_REPL_LOCK   0x80000000 /* Replace DCache Lock */

Definition at line 317 of file armreg.h.

◆ FC_DCACHE_STREAM_EN

#define FC_DCACHE_STREAM_EN   0x20000000 /* DCache Streaming Switch */

Definition at line 318 of file armreg.h.

◆ FC_GLOB_HIST_REG_EN

#define FC_GLOB_HIST_REG_EN   0x00040000 /* Branch Global History Register Enable */

Definition at line 324 of file armreg.h.

◆ FC_ICACHE_REPL_LOCK

#define FC_ICACHE_REPL_LOCK   0x00080000 /* Replace ICache Lock */

Definition at line 323 of file armreg.h.

◆ FC_L1_PAR_ERR_EN

#define FC_L1_PAR_ERR_EN   0x00010000 /* L1 Parity Error Enable */

Definition at line 326 of file armreg.h.

◆ FC_L2_INV_EVICT_LINE

#define FC_L2_INV_EVICT_LINE   0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */

Definition at line 321 of file armreg.h.

◆ FC_L2_PREF_DIS

#define FC_L2_PREF_DIS   0x01000000 /* L2 Cache Prefetch Disable */

Definition at line 320 of file armreg.h.

◆ FC_L2CACHE_EN

#define FC_L2CACHE_EN   0x00400000 /* L2 enable */

Definition at line 322 of file armreg.h.

◆ FC_WR_ALLOC_EN

#define FC_WR_ALLOC_EN   0x10000000 /* Enable Write Allocate */

Definition at line 319 of file armreg.h.

◆ I32_bit

#define I32_bit   (1 << 7) /* IRQ disable */

Definition at line 79 of file armreg.h.

◆ IF32_bits

#define IF32_bits   (3 << 6) /* IRQ/FIQ disable */

Definition at line 81 of file armreg.h.

◆ INSN_COND_AL

#define INSN_COND_AL   14 /* Always condition */

Definition at line 433 of file armreg.h.

◆ INSN_COND_CC

#define INSN_COND_CC   3 /* C == 0 */

Definition at line 422 of file armreg.h.

◆ INSN_COND_CS

#define INSN_COND_CS   2 /* C == 1 */

Definition at line 421 of file armreg.h.

◆ INSN_COND_EQ

#define INSN_COND_EQ   0 /* Z == 1 */

Definition at line 419 of file armreg.h.

◆ INSN_COND_GE

#define INSN_COND_GE   10 /* N == V */

Definition at line 429 of file armreg.h.

◆ INSN_COND_GT

#define INSN_COND_GT   12 /* Z == 0 && N == V */

Definition at line 431 of file armreg.h.

◆ INSN_COND_HI

#define INSN_COND_HI   8 /* C == 1 && Z == 0 */

Definition at line 427 of file armreg.h.

◆ INSN_COND_LE

#define INSN_COND_LE   13 /* Z == 1 || N != V */

Definition at line 432 of file armreg.h.

◆ INSN_COND_LS

#define INSN_COND_LS   9 /* C == 0 || Z == 1 */

Definition at line 428 of file armreg.h.

◆ INSN_COND_LT

#define INSN_COND_LT   11 /* N != V */

Definition at line 430 of file armreg.h.

◆ INSN_COND_MASK

#define INSN_COND_MASK   0xf0000000 /* Condition mask */

Definition at line 418 of file armreg.h.

◆ INSN_COND_MI

#define INSN_COND_MI   4 /* N == 1 */

Definition at line 423 of file armreg.h.

◆ INSN_COND_NE

#define INSN_COND_NE   1 /* Z == 0 */

Definition at line 420 of file armreg.h.

◆ INSN_COND_PL

#define INSN_COND_PL   5 /* N == 0 */

Definition at line 424 of file armreg.h.

◆ INSN_COND_VC

#define INSN_COND_VC   7 /* V == 0 */

Definition at line 426 of file armreg.h.

◆ INSN_COND_VS

#define INSN_COND_VS   6 /* V == 1 */

Definition at line 425 of file armreg.h.

◆ INSN_SIZE

#define INSN_SIZE   4 /* Always 4 bytes */

Definition at line 417 of file armreg.h.

◆ L2CTRL_ICPRES

#define L2CTRL_ICPRES   __BIT(23)

Definition at line 490 of file armreg.h.

◆ L2CTRL_NUMCPU

#define L2CTRL_NUMCPU   __BITS(25,24)

Definition at line 489 of file armreg.h.

◆ MPCORE_AUXCTL_DB

#define MPCORE_AUXCTL_DB   0x00000002 /* dynamic branch prediction */

Definition at line 268 of file armreg.h.

◆ MPCORE_AUXCTL_EX

#define MPCORE_AUXCTL_EX   0x00000010 /* exclusive L1/L2 cache */

Definition at line 271 of file armreg.h.

◆ MPCORE_AUXCTL_F

#define MPCORE_AUXCTL_F   0x00000008 /* instruction folding enable */

Definition at line 270 of file armreg.h.

◆ MPCORE_AUXCTL_RS

#define MPCORE_AUXCTL_RS   0x00000001 /* return stack */

Definition at line 267 of file armreg.h.

◆ MPCORE_AUXCTL_SA

#define MPCORE_AUXCTL_SA   0x00000020 /* SMP/AMP */

Definition at line 272 of file armreg.h.

◆ MPCORE_AUXCTL_SB

#define MPCORE_AUXCTL_SB   0x00000004 /* static branch prediction */

Definition at line 269 of file armreg.h.

◆ MPIDR_AFF0

#define MPIDR_AFF0   __BITS(7,0) /* Affinity Level 0 */

Definition at line 549 of file armreg.h.

◆ MPIDR_AFF1

#define MPIDR_AFF1   __BITS(15,8) /* Affinity Level 1 */

Definition at line 548 of file armreg.h.

◆ MPIDR_AFF2

#define MPIDR_AFF2   __BITS(23,16) /* Affinity Level 2 */

Definition at line 547 of file armreg.h.

◆ MPIDR_MP

#define MPIDR_MP   __BIT(31) /* 1 = Have MP Extention */

Definition at line 544 of file armreg.h.

◆ MPIDR_MT

#define MPIDR_MT   __BIT(24) /* 1 = SMT(AFF0 is logical) */

Definition at line 546 of file armreg.h.

◆ MPIDR_U

#define MPIDR_U   __BIT(30) /* 1 = Uni-Processor System */

Definition at line 545 of file armreg.h.

◆ NRRR_IRn

#define NRRR_IRn (   n)    __BITS(1+2*(n),0+2*(n))

Definition at line 528 of file armreg.h.

◆ NRRR_NC

#define NRRR_NC   0

Definition at line 529 of file armreg.h.

◆ NRRR_ORn

#define NRRR_ORn (   n)    __BITS(17+2*(n),16+2*(n))

Definition at line 527 of file armreg.h.

◆ NRRR_WB

#define NRRR_WB   3

Definition at line 532 of file armreg.h.

◆ NRRR_WB_WA

#define NRRR_WB_WA   1

Definition at line 530 of file armreg.h.

◆ NRRR_WT

#define NRRR_WT   2

Definition at line 531 of file armreg.h.

◆ NSACR_ASEDIS

#define NSACR_ASEDIS   0x00008000 /* Deny Advanced SIMD Ext. */

Definition at line 231 of file armreg.h.

◆ NSACR_CPn

#define NSACR_CPn (   n)    (1 << (n)) /* NonSecure access allowed */

Definition at line 233 of file armreg.h.

◆ NSACR_D32DIS

#define NSACR_D32DIS   0x00004000 /* Deny VFP regs 15-31 */

Definition at line 232 of file armreg.h.

◆ NSACR_L2ERR

#define NSACR_L2ERR   0x00020000 /* L2ECTRL is writeable (!A8) */

Definition at line 230 of file armreg.h.

◆ NSACR_SMP

#define NSACR_SMP   0x00040000 /* ACTRL.SMP is writeable (!A8) */

Definition at line 229 of file armreg.h.

◆ PJ4B_AUXCTL_FW

#define PJ4B_AUXCTL_FW   __BIT(0) /* Cache and TLB updates broadcast */

Definition at line 275 of file armreg.h.

◆ PJ4B_AUXCTL_L1PARITY

#define PJ4B_AUXCTL_L1PARITY   __BIT(9) /* L1 parity checking */

Definition at line 277 of file armreg.h.

◆ PJ4B_AUXCTL_SMPNAMP

#define PJ4B_AUXCTL_SMPNAMP   __BIT(6) /* 0 = AMP, 1 = SMP */

Definition at line 276 of file armreg.h.

◆ PJ4B_AUXFMC0_DCSLFD

#define PJ4B_AUXFMC0_DCSLFD   __BIT(2) /* Disable DC Speculative linefill */

Definition at line 283 of file armreg.h.

◆ PJ4B_AUXFMC0_FW

#define PJ4B_AUXFMC0_FW   __BIT(8) /* alias of PJ4B_AUXCTL_FW*/

Definition at line 284 of file armreg.h.

◆ PJ4B_AUXFMC0_L1PARITY

#define PJ4B_AUXFMC0_L1PARITY   __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */

Definition at line 282 of file armreg.h.

◆ PJ4B_AUXFMC0_L2EN

#define PJ4B_AUXFMC0_L2EN   __BIT(0) /* Tightly-Coupled L2 cache enable */

Definition at line 280 of file armreg.h.

◆ PJ4B_AUXFMC0_SMPNAMP

#define PJ4B_AUXFMC0_SMPNAMP   __BIT(1) /* 0 = AMP, 1 = SMP */

Definition at line 281 of file armreg.h.

◆ PJ4B_MPIDR_CLID

#define PJ4B_MPIDR_CLID   __BITS(11,8) /* AFF1 = cluster id */

Definition at line 561 of file armreg.h.

◆ PJ4B_MPIDR_CPUID

#define PJ4B_MPIDR_CPUID   __BITS(0,3) /* AFF0 = core id */

Definition at line 562 of file armreg.h.

◆ PJ4B_MPIDR_MP

#define PJ4B_MPIDR_MP   MPIDR_MP

Definition at line 558 of file armreg.h.

◆ PJ4B_MPIDR_MT

#define PJ4B_MPIDR_MT   MPIDR_MT /* 1 = SMT(AFF0 is logical) */

Definition at line 560 of file armreg.h.

◆ PJ4B_MPIDR_U

#define PJ4B_MPIDR_U   MPIDR_U

Definition at line 559 of file armreg.h.

◆ PRRR_DS0

#define PRRR_DS0   __BIT(16)

Definition at line 537 of file armreg.h.

◆ PRRR_DS1

#define PRRR_DS1   __BIT(17)

Definition at line 536 of file armreg.h.

◆ PRRR_NOSn

#define PRRR_NOSn (   n)    __BITS(24+2*(n))

Definition at line 533 of file armreg.h.

◆ PRRR_NS0

#define PRRR_NS0   __BIT(18)

Definition at line 535 of file armreg.h.

◆ PRRR_NS1

#define PRRR_NS1   __BIT(19)

Definition at line 534 of file armreg.h.

◆ PRRR_TR_DEVICE

#define PRRR_TR_DEVICE   1

Definition at line 540 of file armreg.h.

◆ PRRR_TR_NORMAL

#define PRRR_TR_NORMAL   2

Definition at line 541 of file armreg.h.

◆ PRRR_TR_STRONG

#define PRRR_TR_STRONG   0

Definition at line 539 of file armreg.h.

◆ PRRR_TRn

#define PRRR_TRn (   n)    __BITS(1+2*(n),0+2*(n))

Definition at line 538 of file armreg.h.

◆ PSR_32_MODE

#define PSR_32_MODE   0x00000010

Definition at line 95 of file armreg.h.

◆ PSR_A_BIT

#define PSR_A_BIT   (1 << 8) /* Async abort disable */

Definition at line 77 of file armreg.h.

◆ PSR_ABT32_MODE

#define PSR_ABT32_MODE   0x00000017

Definition at line 91 of file armreg.h.

◆ PSR_C_bit

#define PSR_C_bit   (1 << 29) /* carry */

Definition at line 62 of file armreg.h.

◆ PSR_E_BIT

#define PSR_E_BIT   (1 << 9) /* Endian state */

Definition at line 76 of file armreg.h.

◆ PSR_FIQ32_MODE

#define PSR_FIQ32_MODE   0x00000011

Definition at line 87 of file armreg.h.

◆ PSR_FLAGS

#define PSR_FLAGS   0xf0000000 /* flags */

Definition at line 59 of file armreg.h.

◆ PSR_GE_bits

#define PSR_GE_bits   (15 << 16) /* SIMD GE bits */

Definition at line 69 of file armreg.h.

◆ PSR_HYP32_MODE

#define PSR_HYP32_MODE   0x0000001a

Definition at line 92 of file armreg.h.

◆ PSR_IRQ32_MODE

#define PSR_IRQ32_MODE   0x00000012

Definition at line 88 of file armreg.h.

◆ PSR_IT0_bit

#define PSR_IT0_bit   (1 << 25)

Definition at line 67 of file armreg.h.

◆ PSR_IT1_bit

#define PSR_IT1_bit   (1 << 26)

Definition at line 66 of file armreg.h.

◆ PSR_IT2_bit

#define PSR_IT2_bit   (1 << 10)

Definition at line 75 of file armreg.h.

◆ PSR_IT3_bit

#define PSR_IT3_bit   (1 << 11)

Definition at line 74 of file armreg.h.

◆ PSR_IT4_bit

#define PSR_IT4_bit   (1 << 12)

Definition at line 73 of file armreg.h.

◆ PSR_IT5_bit

#define PSR_IT5_bit   (1 << 13)

Definition at line 72 of file armreg.h.

◆ PSR_IT6_bit

#define PSR_IT6_bit   (1 << 14)

Definition at line 71 of file armreg.h.

◆ PSR_IT7_bit

#define PSR_IT7_bit   (1 << 15)

Definition at line 70 of file armreg.h.

◆ PSR_J_bit

#define PSR_J_bit   (1 << 24) /* Jazelle mode */

Definition at line 68 of file armreg.h.

◆ PSR_MODE

#define PSR_MODE   0x0000001f /* mode mask */

Definition at line 85 of file armreg.h.

◆ PSR_MON32_MODE

#define PSR_MON32_MODE   0x00000016

Definition at line 90 of file armreg.h.

◆ PSR_N_bit

#define PSR_N_bit   (1 << 31) /* negative */

Definition at line 60 of file armreg.h.

◆ PSR_Q_bit

#define PSR_Q_bit   (1 << 27) /* saturation */

Definition at line 65 of file armreg.h.

◆ PSR_SVC32_MODE

#define PSR_SVC32_MODE   0x00000013

Definition at line 89 of file armreg.h.

◆ PSR_SYS32_MODE

#define PSR_SYS32_MODE   0x0000001f

Definition at line 94 of file armreg.h.

◆ PSR_T_bit

#define PSR_T_bit   (1 << 5) /* Thumb state */

Definition at line 83 of file armreg.h.

◆ PSR_UND32_MODE

#define PSR_UND32_MODE   0x0000001b

Definition at line 93 of file armreg.h.

◆ PSR_USR32_MODE

#define PSR_USR32_MODE   0x00000010

Definition at line 86 of file armreg.h.

◆ PSR_V_bit

#define PSR_V_bit   (1 << 28) /* overflow */

Definition at line 63 of file armreg.h.

◆ PSR_Z_bit

#define PSR_Z_bit   (1 << 30) /* zero */

Definition at line 61 of file armreg.h.

◆ R15_FLAG_C

#define R15_FLAG_C   0x20000000

Definition at line 100 of file armreg.h.

◆ R15_FLAG_N

#define R15_FLAG_N   0x80000000

Definition at line 98 of file armreg.h.

◆ R15_FLAG_V

#define R15_FLAG_V   0x10000000

Definition at line 101 of file armreg.h.

◆ R15_FLAG_Z

#define R15_FLAG_Z   0x40000000

Definition at line 99 of file armreg.h.

◆ R15_FLAGS

#define R15_FLAGS   0xf0000000

Definition at line 97 of file armreg.h.

◆ THUMB_INSN_SIZE

#define THUMB_INSN_SIZE   2 /* Some are 4 bytes. */

Definition at line 435 of file armreg.h.

◆ TTBCR_L_A1

#define TTBCR_L_A1   __BIT(22)

Definition at line 519 of file armreg.h.

◆ TTBCR_L_EAE

#define TTBCR_L_EAE   __BIT(31)

Definition at line 514 of file armreg.h.

◆ TTBCR_L_EPD0

#define TTBCR_L_EPD0   __BIT(7)

Definition at line 524 of file armreg.h.

◆ TTBCR_L_EPD1

#define TTBCR_L_EPD1   __BIT(23)

Definition at line 518 of file armreg.h.

◆ TTBCR_L_IRGN0

#define TTBCR_L_IRGN0   __BITS(9,8)

Definition at line 523 of file armreg.h.

◆ TTBCR_L_IRGN1

#define TTBCR_L_IRGN1   __BITS(25,24)

Definition at line 517 of file armreg.h.

◆ TTBCR_L_ORGN0

#define TTBCR_L_ORGN0   __BITS(11,10)

Definition at line 522 of file armreg.h.

◆ TTBCR_L_ORGN1

#define TTBCR_L_ORGN1   __BITS(27,26)

Definition at line 516 of file armreg.h.

◆ TTBCR_L_SH0

#define TTBCR_L_SH0   __BITS(13,12)

Definition at line 521 of file armreg.h.

◆ TTBCR_L_SH1

#define TTBCR_L_SH1   __BITS(29,28)

Definition at line 515 of file armreg.h.

◆ TTBCR_L_T0SZ

#define TTBCR_L_T0SZ   __BITS(2,0)

Definition at line 525 of file armreg.h.

◆ TTBCR_L_T1SZ

#define TTBCR_L_T1SZ   __BITS(18,16)

Definition at line 520 of file armreg.h.

◆ TTBCR_S_EAE

#define TTBCR_S_EAE   __BIT(31)

Definition at line 509 of file armreg.h.

◆ TTBCR_S_N

#define TTBCR_S_N   __BITS(2,0)

Definition at line 512 of file armreg.h.

◆ TTBCR_S_PD0

#define TTBCR_S_PD0   __BIT(4)

Definition at line 511 of file armreg.h.

◆ TTBCR_S_PD1

#define TTBCR_S_PD1   __BIT(5)

Definition at line 510 of file armreg.h.

◆ TTBR_C

#define TTBR_C   __BIT(0) /* without MPE */

Definition at line 493 of file armreg.h.

◆ TTBR_IMP

#define TTBR_IMP   __BIT(2)

Definition at line 495 of file armreg.h.

◆ TTBR_IRGN_MASK

#define TTBR_IRGN_MASK   (__BIT(6) | __BIT(0))

Definition at line 502 of file armreg.h.

◆ TTBR_IRGN_NC

#define TTBR_IRGN_NC   0

Definition at line 503 of file armreg.h.

◆ TTBR_IRGN_WBNWA

#define TTBR_IRGN_WBNWA   (__BIT(0) | __BIT(6))

Definition at line 506 of file armreg.h.

◆ TTBR_IRGN_WBWA

#define TTBR_IRGN_WBWA   __BIT(6)

Definition at line 504 of file armreg.h.

◆ TTBR_IRGN_WT

#define TTBR_IRGN_WT   __BIT(0)

Definition at line 505 of file armreg.h.

◆ TTBR_NOS

#define TTBR_NOS   __BIT(5)

Definition at line 501 of file armreg.h.

◆ TTBR_RGN_MASK

#define TTBR_RGN_MASK   __BITS(4,3)

Definition at line 496 of file armreg.h.

◆ TTBR_RGN_NC

#define TTBR_RGN_NC   __SHIFTIN(0, TTBR_RGN_MASK)

Definition at line 497 of file armreg.h.

◆ TTBR_RGN_WBNWA

#define TTBR_RGN_WBNWA   __SHIFTIN(3, TTBR_RGN_MASK)

Definition at line 500 of file armreg.h.

◆ TTBR_RGN_WBWA

#define TTBR_RGN_WBWA   __SHIFTIN(1, TTBR_RGN_MASK)

Definition at line 498 of file armreg.h.

◆ TTBR_RGN_WT

#define TTBR_RGN_WT   __SHIFTIN(2, TTBR_RGN_MASK)

Definition at line 499 of file armreg.h.

◆ TTBR_S

#define TTBR_S   __BIT(1)

Definition at line 494 of file armreg.h.

◆ XSCALE_AUXCTL_K

#define XSCALE_AUXCTL_K   0x00000001 /* dis. write buffer coalescing */

Definition at line 259 of file armreg.h.

◆ XSCALE_AUXCTL_MD_MASK

#define XSCALE_AUXCTL_MD_MASK   0x00000030

Definition at line 264 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WB_RA

#define XSCALE_AUXCTL_MD_WB_RA   0x00000000 /* mini-D$ wb, read-allocate */

Definition at line 261 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WB_RWA

#define XSCALE_AUXCTL_MD_WB_RWA   0x00000010 /* mini-D$ wb, read/write-allocate */

Definition at line 262 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WT

#define XSCALE_AUXCTL_MD_WT   0x00000020 /* mini-D$ wt, read-allocate */

Definition at line 263 of file armreg.h.

◆ XSCALE_AUXCTL_P

#define XSCALE_AUXCTL_P   0x00000002 /* ECC protect page table access */

Definition at line 260 of file armreg.h.

Function Documentation

◆ ARMREG_READ64_INLINE() [1/5]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ64_INLINE ( cntp_ct  ,
p15,
,
Q0,
R0,
c14  
)

◆ ARMREG_READ64_INLINE() [2/5]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 ARMREG_READ64_INLINE ( cntp_cval  ,
p15,
,
Q0,
R0,
c14  
)

◆ ARMREG_READ64_INLINE() [3/5]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 ARMREG_READ64_INLINE ( cntv_ct  ,
p15,
,
Q0,
R0,
c14  
)

◆ ARMREG_READ64_INLINE() [4/5]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 ARMREG_READ64_INLINE ( cntv_cval  ,
p15,
,
Q0,
R0,
c14  
)

◆ ARMREG_READ64_INLINE() [5/5]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 ARMREG_READ64_INLINE ( cntvoff  ,
p15,
,
Q0,
R0,
c14  
)

◆ ARMREG_READ_INLINE() [1/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( auxctl  ,
p15,
,
0,
c1  ,
c0  ,
1"   
)

◆ ARMREG_READ_INLINE() [2/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_READ_INLINE ( cbar  ,
p15,
,
0,
c15  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [3/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( ccsidr  ,
p15,
,
0,
c0  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [4/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cnt_frq  ,
p15,
,
0,
c14  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [5/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cntk_ctl  ,
p15,
,
0,
c14  ,
c1  ,
0"   
)

◆ ARMREG_READ_INLINE() [6/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cntp_ctl  ,
p15,
,
0,
c14  ,
c2  ,
1"   
)

◆ ARMREG_READ_INLINE() [7/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cntp_tval  ,
p15,
,
0,
c14  ,
c2  ,
0"   
)

◆ ARMREG_READ_INLINE() [8/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cntv_ctl  ,
p15,
,
0,
c14  ,
c3  ,
1"   
)

◆ ARMREG_READ_INLINE() [9/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cntv_tval  ,
p15,
,
0,
c14  ,
c3  ,
0"   
)

◆ ARMREG_READ_INLINE() [10/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( contextidr  ,
p15,
,
0,
c13  ,
c0  ,
1"   
)

◆ ARMREG_READ_INLINE() [11/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( cpacr  ,
p15,
,
0,
c1  ,
c0  ,
2"   
)

◆ ARMREG_READ_INLINE() [12/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( csselr  ,
p15,
,
0,
c0  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [13/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( ctr  ,
p15,
,
0,
c0  ,
c0  ,
1"   
)

◆ ARMREG_READ_INLINE() [14/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( dacr  ,
p15,
,
0,
c3  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [15/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( dfar  ,
p15,
,
0,
c6  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [16/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( dfsr  ,
p15,
,
0,
c5  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [17/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( isar0  ,
p15,
,
0,
c0  ,
c2  ,
0"   
)

◆ ARMREG_READ_INLINE() [18/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( isar2  ,
p15,
,
0,
c0  ,
c2  ,
2"   
)

◆ ARMREG_READ_INLINE() [19/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( isar4  ,
p15,
,
0,
c0  ,
c2  ,
4"   
)

◆ ARMREG_READ_INLINE() [20/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( mmfr0  ,
p15,
,
0,
c0  ,
c1  ,
4"   
)

◆ ARMREG_READ_INLINE() [21/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( mmfr2  ,
p15,
,
0,
c0  ,
c1  ,
6"   
)

◆ ARMREG_READ_INLINE() [22/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( mpidr  ,
p15,
,
0,
c0  ,
c0  ,
5"   
)

◆ ARMREG_READ_INLINE() [23/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( nrrr  ,
p15,
,
0,
c10  ,
c2  ,
1"   
)

◆ ARMREG_READ_INLINE() [24/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( par  ,
p15,
,
0,
c7  ,
c4  ,
0"   
)

◆ ARMREG_READ_INLINE() [25/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( pfr0  ,
p15,
,
0,
c0  ,
c1  ,
0"   
)

◆ ARMREG_READ_INLINE() [26/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( pmceid1  ,
p15,
,
0,
c9  ,
c12  ,
7"   
)

◆ ARMREG_READ_INLINE() [27/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( prrr  ,
p15,
,
0,
c10  ,
c2  ,
0"   
)

◆ ARMREG_READ_INLINE() [28/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( scr  ,
p15,
,
0,
c1  ,
c1  ,
0"   
)

◆ ARMREG_READ_INLINE() [29/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( sctlr  ,
p15,
,
0,
c1  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [30/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_READ_INLINE ( tlbdata1  ,
p15,
,
0,
c15  ,
c0  ,
1"   
)

◆ ARMREG_READ_INLINE() [31/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( tpidrprw  ,
p15,
,
0,
c13  ,
c0  ,
4"   
)

◆ ARMREG_READ_INLINE() [32/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( tpidruro  ,
p15,
,
0,
c13  ,
c0  ,
3"   
)

◆ ARMREG_READ_INLINE() [33/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( tpidrurw  ,
p15,
,
0,
c13  ,
c0  ,
2"   
)

◆ ARMREG_READ_INLINE() [34/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( ttbcr  ,
p15,
,
0,
c2  ,
c0  ,
2"   
)

◆ ARMREG_READ_INLINE() [35/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( ttbr  ,
p15,
,
0,
c2  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE() [36/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( ttbr1  ,
p15,
,
0,
c2  ,
c0  ,
1"   
)

◆ ARMREG_READ_INLINE() [37/37]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_READ_INLINE ( vbar  ,
p15,
,
0,
c12  ,
c0  ,
0"   
)

◆ ARMREG_READ_INLINE2() [1/2]

ARMREG_READ_INLINE2 ( fpsid  ,
"vmrs\t%  0,
fpsid"   
)

◆ ARMREG_READ_INLINE2() [2/2]

vmrs fpscr vmrs mvfr1 ARMREG_READ_INLINE2 ( mvfr0  ,
"vmrs\t%  0,
mvfr0"   
)

◆ ARMREG_WRITE_INLINE() [1/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( ats1cpr  ,
p15,
,
0,
c7  ,
c8  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [2/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( ats1cur  ,
p15,
,
0,
c7  ,
c8  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [3/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( bpiall  ,
p15,
,
0,
c7  ,
c5  ,
6"   
)

◆ ARMREG_WRITE_INLINE() [4/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dccisw  ,
p15,
,
0,
c7  ,
c14  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [5/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dccmvac  ,
p15,
,
0,
c7  ,
c10  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [6/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dccmvau  ,
p15,
,
0,
c7  ,
c11  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [7/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dcimvac  ,
p15,
,
0,
c7  ,
c6  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [8/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dsb  ,
p15,
,
0,
c7  ,
c10  ,
4"   
)

◆ ARMREG_WRITE_INLINE() [9/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dtlbiall  ,
p15,
,
0,
c8  ,
c6  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [10/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( dtlbiasid  ,
p15,
,
0,
c8  ,
c6  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [11/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( icialluis  ,
p15,
,
0,
c7  ,
c1  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [12/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( icimvau  ,
p15,
,
0,
c7  ,
c5  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [13/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( itlbimva  ,
p15,
,
0,
c8  ,
c5  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [14/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmccntr  ,
p15,
,
0,
c9  ,
c13  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [15/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE ( pmccntrv6  ,
p15,
,
0,
c15  ,
c12  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [16/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmcntenclr  ,
p15,
,
0,
c9  ,
c12  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [17/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmcntenset  ,
p15,
,
0,
c9  ,
c12  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [18/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmcr  ,
p15,
,
0,
c9  ,
c12  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [19/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE ( pmcrv6  ,
p15,
,
0,
c15  ,
c12  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [20/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmintenclr  ,
p15,
,
0,
c9  ,
c14  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [21/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmintenset  ,
p15,
,
0,
c9  ,
c14  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [22/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmovsr  ,
p15,
,
0,
c9  ,
c12  ,
3"   
)

◆ ARMREG_WRITE_INLINE() [23/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmselr  ,
p15,
,
0,
c9  ,
c12  ,
5"   
)

◆ ARMREG_WRITE_INLINE() [24/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmuserenr  ,
p15,
,
0,
c9  ,
c14  ,
0"   
)

◆ ARMREG_WRITE_INLINE() [25/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmxevcntr  ,
p15,
,
0,
c9  ,
c13  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [26/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( pmxevtyper  ,
p15,
,
0,
c9  ,
c13  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [27/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 ARMREG_WRITE_INLINE ( tlbdataop  ,
p15,
,
0,
c15  ,
c4  ,
2"   
)

◆ ARMREG_WRITE_INLINE() [28/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( tlbimva  ,
p15,
,
0,
c8  ,
c7  ,
1"   
)

◆ ARMREG_WRITE_INLINE() [29/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( tlbimvaa  ,
p15,
,
0,
c8  ,
c7  ,
3"   
)

◆ ARMREG_WRITE_INLINE() [30/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( tlbimvaais  ,
p15,
,
0,
c8  ,
c3  ,
3"   
)

◆ ARMREG_WRITE_INLINE() [31/31]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE ( tlbimvais  ,
p15,
,
0,
c8  ,
c3  ,
1"   
)

◆ ARMREG_WRITE_INLINE2() [1/4]

vmrs fpscr vmrs mvfr1 vmrs fpexc ARMREG_WRITE_INLINE2 ( fpexc  ,
"vmsr\  tfpexc,
%0"   
)

◆ ARMREG_WRITE_INLINE2() [2/4]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst ARMREG_WRITE_INLINE2 ( fpinst  ,
"fmxr\  tfpinst,
%0"   
)

◆ ARMREG_WRITE_INLINE2() [3/4]

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 ARMREG_WRITE_INLINE2 ( fpinst2  ,
"fmxr\  tfpinst2,
%0"   
)

◆ ARMREG_WRITE_INLINE2() [4/4]

vmrs fpscr ARMREG_WRITE_INLINE2 ( fpscr  ,
"vmsr\  tfpscr,
%0"   
)

Variable Documentation

◆ c0

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 c0

Definition at line 762 of file armreg.h.

◆ c1

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 c1

Definition at line 768 of file armreg.h.

◆ c10

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c10

Definition at line 824 of file armreg.h.

◆ c12

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 c12

Definition at line 846 of file armreg.h.

◆ c13

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c13

Definition at line 858 of file armreg.h.

◆ c14

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14

Definition at line 828 of file armreg.h.

◆ c15

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 c15

Definition at line 914 of file armreg.h.

◆ c2

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c2

Definition at line 774 of file armreg.h.

◆ c3

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c3

Definition at line 801 of file armreg.h.

◆ c5

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c5

Definition at line 804 of file armreg.h.

◆ c6

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c6

Definition at line 807 of file armreg.h.

◆ c7

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c7

Definition at line 810 of file armreg.h.

◆ c8

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c8

Definition at line 820 of file armreg.h.

◆ c9

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c9

Definition at line 846 of file armreg.h.

◆ p15

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 c14 p15

Definition at line 762 of file armreg.h.

◆ Q0

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 Q0

Definition at line 903 of file armreg.h.

◆ R0

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c14 c14 c14 c14 R0

Definition at line 903 of file armreg.h.

◆ t

vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx t

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