alpha_rpb.h Source File
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41 #define HWRPB_ADDR 0x10000000
44 #define PROM_ENTRY_PADDR 0x10000
45 #define PROM_ARGSPACE_PADDR 0x12000
46 #define HWRPB_PADDR 0x14000
47 #define CTB_ADDR (HWRPB_ADDR + 0x1000)
48 #define CRB_ADDR (HWRPB_ADDR + 0x1400)
49 #define MEMDAT_ADDR (HWRPB_ADDR + 0x1800)
50 #define PCS_ADDR (HWRPB_ADDR + 0x1c00)
68 #define ST_DEC_3000_500 4
69 #define ST_DEC_2000_300 6
70 #define ST_DEC_3000_300 7
71 #define ST_AVALON_A12 8
72 #define ST_DEC_2100_A500 9
73 #define ST_DEC_APXVME_64 10
74 #define ST_DEC_AXPPCI_33 11
75 #define ST_DEC_21000 12
76 #define ST_DEC_2100_A50 13
77 #define ST_DEC_MUSTANG 14
78 #define ST_DEC_KN20AA 15
79 #define ST_DEC_1000 17
82 #define ST_ALPHABOOK1 21
83 #define ST_DEC_4100 22
84 #define ST_DEC_EV45_PBP 23
85 #define ST_DEC_2100A_A500 24
87 #define ST_DEC_1000A 27
88 #define ST_DEC_ALPHAVME_224 28
90 #define ST_DEC_EV56_PBP 32
91 #define ST_DEC_ALPHAVME_320 33
92 #define ST_DEC_6600 34
93 #define ST_DEC_WILDFIRE 35
94 #define ST_DEC_CUSCO 36
95 #define ST_DEC_EIGER 37
96 #define ST_DEC_TITAN 38
99 #define ST_API_NAUTILUS 201
103 #define SV_MPCAP 0x00000001
105 #define SV_CONSOLE 0x0000001e
106 #define SV_CONSOLE_DETACHED 0x00000002
107 #define SV_CONSOLE_EMBEDDED 0x00000004
109 #define SV_POWERFAIL 0x000000e0
110 #define SV_PF_UNITED 0x00000020
111 #define SV_PF_SEPARATE 0x00000040
112 #define SV_PF_BBACKUP 0x00000060
113 #define SV_PF_ACTION 0x00000100
115 #define SV_GRAPHICS 0x00000200
117 #define SV_ST_MASK 0x0000fc00
118 #define SV_ST_RESERVED 0x00000000
123 #define SV_ST_SANDPIPER 0x00000400
124 #define SV_ST_FLAMINGO 0x00000800
125 #define SV_ST_HOTPINK 0x00000c00
126 #define SV_ST_FLAMINGOPLUS 0x00001000
127 #define SV_ST_ULTRA 0x00001400
128 #define SV_ST_SANDPLUS 0x00001800
129 #define SV_ST_SANDPIPER45 0x00001c00
130 #define SV_ST_FLAMINGO45 0x00002000
135 #define SV_ST_SABLE 0x00000400
140 #define SV_ST_PELICAN 0x00000000
141 #define SV_ST_PELICA 0x00000400
142 #define SV_ST_PELICANPLUS 0x00000800
143 #define SV_ST_PELICAPLUS 0x00000c00
148 #define SV_ST_AVANTI 0x00000000
149 #define SV_ST_MUSTANG2_4_166 0x00000800
150 #define SV_ST_MUSTANG2_4_233 0x00001000
151 #define SV_ST_AVANTI_XXX 0x00001400
152 #define SV_ST_AVANTI_4_266 0x00002000
153 #define SV_ST_MUSTANG2_4_100 0x00002400
154 #define SV_ST_AVANTI_4_233 0x0000a800
156 #define SV_ST_KN20AA 0x00000400
161 #define SV_ST_AXPVME_64 0x00000000
162 #define SV_ST_AXPVME_160 0x00000400
163 #define SV_ST_AXPVME_100 0x00000c00
164 #define SV_ST_AXPVME_230 0x00001000
165 #define SV_ST_AXPVME_66 0x00001400
166 #define SV_ST_AXPVME_166 0x00001800
167 #define SV_ST_AXPVME_264 0x00001c00
172 #define SV_ST_EB164_266 0x00000400
173 #define SV_ST_EB164_300 0x00000800
174 #define SV_ST_ALPHAPC164_366 0x00000c00
175 #define SV_ST_ALPHAPC164_400 0x00001000
176 #define SV_ST_ALPHAPC164_433 0x00001400
177 #define SV_ST_ALPHAPC164_466 0x00001800
178 #define SV_ST_ALPHAPC164_500 0x00001c00
179 #define SV_ST_ALPHAPC164LX_400 0x00002000
180 #define SV_ST_ALPHAPC164LX_466 0x00002400
181 #define SV_ST_ALPHAPC164LX_533 0x00002800
182 #define SV_ST_ALPHAPC164LX_600 0x00002c00
183 #define SV_ST_ALPHAPC164SX_400 0x00003000
184 #define SV_ST_ALPHAPC164SX_466 0x00003400
185 #define SV_ST_ALPHAPC164SX_533 0x00003800
186 #define SV_ST_ALPHAPC164SX_600 0x00003c00
192 #define SV_ST_MIATA_1_5 0x00004c00
227 #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \
228 ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size)))
236 #define PCS_BIP 0x000001
237 #define PCS_RC 0x000002
238 #define PCS_PA 0x000004
239 #define PCS_PP 0x000008
240 #define PCS_OH 0x000010
241 #define PCS_CV 0x000020
242 #define PCS_PV 0x000040
243 #define PCS_PMV 0x000080
244 #define PCS_PL 0x000100
246 #define PCS_HALT_REQ 0xff0000
247 #define PCS_HALT_DEFAULT 0x000000
248 #define PCS_HALT_SAVE_EXIT 0x010000
249 #define PCS_HALT_COLD_BOOT 0x020000
250 #define PCS_HALT_WARM_BOOT 0x030000
251 #define PCS_HALT_STAY_HALTED 0x040000
252 #define PCS_mbz 0xffffffffff000000
263 #define PAL_TYPE_STANDARD 0
264 #define PAL_TYPE_VMS 1
265 #define PAL_TYPE_OSF1 2
277 #define pcs_minorrev pcs_pal_rev.minorrev
278 #define pcs_majorrev pcs_pal_rev.majorrev
279 #define pcs_pal_type pcs_pal_rev.pal_type
280 #define pcs_compatibility pcs_pal_rev.compatibility
281 #define pcs_proc_cnt pcs_pal_rev.proc_cnt
285 #define PCS_PROC_EV3 1
286 #define PCS_PROC_EV4 2
287 #define PCS_PROC_SIMULATION 3
288 #define PCS_PROC_LCA4 4
289 #define PCS_PROC_EV5 5
290 #define PCS_PROC_EV45 6
291 #define PCS_PROC_EV56 7
292 #define PCS_PROC_EV6 8
293 #define PCS_PROC_PCA56 9
294 #define PCS_PROC_PCA57 10
295 #define PCS_PROC_EV67 11
296 #define PCS_PROC_EV68CB 12
297 #define PCS_PROC_EV68AL 13
298 #define PCS_PROC_EV68CX 14
300 #define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff)
301 #define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32)
307 #define PCS_VAR_VAXFP 0x0000000000000001
308 #define PCS_VAR_IEEEFP 0x0000000000000002
309 #define PCS_VAR_PE 0x0000000000000004
310 #define PCS_VAR_RESERVED 0xfffffffffffffff8
323 #define PCS_HALT_RESERVED 0
324 #define PCS_HALT_POWERUP 1
325 #define PCS_HALT_CONSOLE_HALT 2
326 #define PCS_HALT_CONSOLE_CRASH 3
327 #define PCS_HALT_KERNEL_MODE 4
328 #define PCS_HALT_KERNEL_STACK_INVALID 5
329 #define PCS_HALT_DOUBLE_ERROR_ABORT 6
330 #define PCS_HALT_SCBB 7
331 #define PCS_HALT_PTBR 8
343 #define PALvar_reserved 0
344 #define PALvar_OpenVMS 1
345 #define PALvar_OSF1 2
363 #define CTB_NONE 0x00
364 #define CTB_SERVICE 0x01
365 #define CTB_PRINTERPORT 0x02
366 #define CTB_GRAPHICS 0x03
367 #define CTB_TYPE4 0x04
368 #define CTB_NETWORK 0xC0
419 #define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff)
420 #define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff)
421 #define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff)
422 #define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff)
423 #define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff)
425 #define CTB_TURBOSLOT_TYPE_TC 0
426 #define CTB_TURBOSLOT_TYPE_ISA 1
427 #define CTB_TURBOSLOT_TYPE_EISA 2
428 #define CTB_TURBOSLOT_TYPE_PCI 3
463 #define MDDT_NONVOLATILE 0x10
464 #define MDDT_PALCODE 0x01
465 #define MDDT_SYSTEM 0x00
466 #define MDDT_mbz 0xfffffffffffffffc
496 #define HWRPB_DSRDB_MINVERS 5
500 extern struct rpb *hwrpb;
u_int64_t dsr_sysname_off
u_int64_t rpb_restart_val
struct mddt_cluster mddt_clusters[2]
u_int64_t pcs_pal_memaddr
u_int64_t pcs_pal_scrsize
char pcs_proc_revision[8]
u_int64_t rpb_save_term_val
u_int64_t ctb_keybd_trans
u_int32_t rpb_extended_va_size
u_int64_t pcs_machcheck_len
u_int64_t pcs_pal_memsize
u_int64_t pcs_reserved_soft
u_int64_t pcs_reserved_arch[6]
u_int64_t rpb_reserved_arch
u_int64_t rpb_rest_term_val
u_int32_t rpb_phys_addr_size
u_int64_t ctb_listen_state
struct pcs::@4 pcs_pal_rev
u_int64_t ctb_font_height
u_int64_t mddt_cluster_cnt
u_int64_t pcs_palrevisions[16]
u_int64_t ctb_head_offset
u_int64_t ctb_keybd_state
u_int64_t pcs_pal_scraddr
u_int64_t rpb_primary_cpu_id
u_int64_t pcs_halt_reason
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