dev_ohci.cc Source File

Back to the index.

dev_ohci.cc
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2004-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: USB Open Host Controller Interface
29  *
30  * TODO
31  */
32 
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 
37 #include "cpu.h"
38 #include "device.h"
39 #include "interrupt.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43 
44 #include "thirdparty/ohcireg.h"
45 
46 
47 /* Length is 0x1000 at least on Playstation 2 */
48 #define DEV_OHCI_LENGTH 0x1000
49 
50 
51 #define debug fatal
52 
53 
54 struct ohci_data {
55  struct interrupt irq;
56 
58 };
59 
60 
62 {
63  struct ohci_data *d = (struct ohci_data *) extra;
64  uint64_t idata = 0, odata = 0;
65  const char *name = NULL;
66 
67  if (writeflag == MEM_WRITE)
68  idata = memory_readmax64(cpu, data, len);
69 
70  switch (relative_addr) {
71  case OHCI_REVISION:
72  name = "REVISION";
73  if (writeflag == MEM_READ) {
74  odata = 0x10; /* Version 1.0. */
75  }
76  break;
78  name = "COMMAND_STATUS";
79  if (idata == 0x2) {
80  fatal("Hm... OHCI COMMAND STATUS\n");
82  }
83  break;
85  name = "INTERRUPT_STATUS";
86  odata = OHCI_WDH;
87  break;
88 /*
89  * TODO: It now sleeps at tsleep(xfer, PRIBIO, "usbsyn", 0);
90  * in netbsd/src/sys/dev/usb/usbdi.c
91  */
93  name = "RH_DESCRIPTOR_A";
94  odata = 2; /* Nr of ports */
95  break;
96  case OHCI_RH_STATUS:
97  name = "RH_STATUS";
98  /* TODO */
99  break;
100  case OHCI_RH_PORT_STATUS(1): /* First port */
101  name = "RH_PORT_STATUS(1)";
102  if (writeflag == MEM_READ) {
103  /* Status = low 16, Change = top 16 */
104  odata = 0x10101;
105  /* 0x0001 = connected
106  0x0100 = power */
107  if (d->port1reset)
108  odata |= (0x10 << 16) | 0x10;
109  } else {
110  /* 0x10 = UPS_C_PORT_RESET */
111  if (idata & 0x10)
112  d->port1reset = 1;
113  if (idata & 0x100000)
114  d->port1reset = 0;
115  }
116  break;
117  case OHCI_RH_PORT_STATUS(2): /* Second port */
118  name = "RH_PORT_STATUS(2)";
119  /* TODO */
120  odata = 0;
121  break;
122  default:
123  if (writeflag == MEM_READ) {
124  debug("[ ohci: read from addr 0x%x: 0x%llx ]\n",
125  (int)relative_addr, (long long)odata);
126  } else {
127  debug("[ ohci: write to addr 0x%x: 0x%llx ]\n",
128  (int)relative_addr, (long long)idata);
129  }
130  }
131 
132  if (name != NULL) {
133  if (writeflag == MEM_READ)
134  debug("[ ohci: read from %s: 0x%llx ]\n",
135  name, (long long)odata);
136  else
137  debug("[ ohci: write to %s: 0x%llx ]\n",
138  name, (long long)idata);
139  }
140 
141  if (writeflag == MEM_READ)
142  memory_writemax64(cpu, data, len, odata);
143 
144  return 1;
145 }
146 
147 
148 DEVINIT(ohci)
149 {
150  struct ohci_data *d;
151 
152  CHECK_ALLOCATION(d = (struct ohci_data *) malloc(sizeof(struct ohci_data)));
153  memset(d, 0, sizeof(struct ohci_data));
154 
156 
159  DEV_OHCI_LENGTH, dev_ohci_access, d, DM_DEFAULT, NULL);
160 
161  return 1;
162 }
163 
data
u_short data
Definition: siireg.h:79
DEV_OHCI_LENGTH
#define DEV_OHCI_LENGTH
Definition: dev_ohci.cc:48
OHCI_RH_DESCRIPTOR_A
#define OHCI_RH_DESCRIPTOR_A
Definition: ohcireg.h:108
INTERRUPT_CONNECT
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
INTERRUPT_ASSERT
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
ohcireg.h
devinit::addr
uint64_t addr
Definition: device.h:46
memory_device_register
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
MEM_READ
#define MEM_READ
Definition: memory.h:116
ohci_data::port1reset
int port1reset
Definition: dev_ohci.cc:57
DM_DEFAULT
#define DM_DEFAULT
Definition: memory.h:130
devinit::machine
struct machine * machine
Definition: device.h:41
DEVICE_ACCESS
DEVICE_ACCESS(ohci)
Definition: dev_ohci.cc:61
device.h
MEM_WRITE
#define MEM_WRITE
Definition: memory.h:117
devinit::interrupt_path
char * interrupt_path
Definition: device.h:50
interrupt.h
fatal
void fatal(const char *fmt,...)
Definition: main.cc:152
OHCI_WDH
#define OHCI_WDH
Definition: ohcireg.h:83
misc.h
memory_readmax64
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
machine.h
devinit::name
char * name
Definition: device.h:43
devinit
Definition: device.h:40
OHCI_INTERRUPT_STATUS
#define OHCI_INTERRUPT_STATUS
Definition: ohcireg.h:81
cpu.h
machine::memory
struct memory * memory
Definition: machine.h:126
OHCI_RH_PORT_STATUS
#define OHCI_RH_PORT_STATUS(n)
Definition: ohcireg.h:124
OHCI_REVISION
#define OHCI_REVISION
Definition: ohcireg.h:52
debug
#define debug
Definition: dev_ohci.cc:51
OHCI_RH_STATUS
#define OHCI_RH_STATUS
Definition: ohcireg.h:117
interrupt
Definition: interrupt.h:36
memory_writemax64
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
cpu
Definition: cpu.h:326
ohci_data::irq
struct interrupt irq
Definition: dev_ohci.cc:55
OHCI_COMMAND_STATUS
#define OHCI_COMMAND_STATUS
Definition: ohcireg.h:75
DEVINIT
DEVINIT(ohci)
Definition: dev_ohci.cc:148
memory.h
ohci_data
Definition: dev_ohci.cc:54
CHECK_ALLOCATION
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239

Generated on Tue Mar 24 2020 14:04:48 for GXemul by doxygen 1.8.17