dev_luna88k.cc Source File

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dev_luna88k.cc
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1 /*
2  * Copyright (C) 2018 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: OMRON Luna 88K-specific devices and control registers
29  *
30  * Almost everything in here is just dummy code which returns nonsense,
31  * just enough to fake hardware well enough to get OpenBSD/luna88k to
32  * not stop early during bootup. It does not really work yet.
33  *
34  * TODO: Separate out these devices to their own files, so that they can
35  * potentially be reused for a luna68k mode if necessary.
36  */
37 
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <string.h>
41 
42 #include "cpu.h"
43 #include "console.h"
44 #include "device.h"
45 #include "devices.h"
46 #include "emul.h"
47 #include "machine.h"
48 #include "memory.h"
49 #include "misc.h"
50 
51 #include "thirdparty/sccreg.h" // similar to sio?
54 #include "thirdparty/m8820x.h"
55 
56 #define TICK_STEPS_SHIFT 14
57 
58 
59 #define LUNA88K_REGISTERS_BASE 0x3ffffff0UL
60 #define LUNA88K_REGISTERS_END 0xff000000UL
61 #define LUNA88K_REGISTERS_LENGTH (LUNA88K_REGISTERS_END - LUNA88K_REGISTERS_BASE)
62 
63 #define MAX_CPUS 4
64 
65 
66 #define BCD(x) ((((x) / 10) << 4) + ((x) % 10))
67 
68 
69 struct luna88k_data {
70  struct vfb_data *fb;
71 
73  bool irqActive;
76 
78 
81 
84  struct interrupt irqX;
85 
86  /* Two channels. */
88  uint8_t obio_sio_rr[2][8];
89  uint8_t obio_sio_wr[2][8];
90 
91  uint32_t fuse_rom[FUSE_ROM_SPACE / sizeof(uint32_t)];
92  uint8_t nvram[NVRAM_SPACE];
93 };
94 
95 
96 static void reassert_interrupts(struct luna88k_data *d)
97 {
98  // printf("status = 0x%08x, enable = 0x%08x\n",
99  // d->interrupt_status[0], d->interrupt_enable[0]);
100 
101  if (d->interrupt_status[0] & d->interrupt_enable[0]) {
102  if (!d->irqActive)
104 
105  d->irqActive = true;
106  } else {
107  if (d->irqActive)
109 
110  d->irqActive = false;
111  }
112 }
113 
114 static void luna88k_interrupt_assert(struct interrupt *interrupt)
115 {
116  struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
117  d->interrupt_status[0] |= (1 << (interrupt->line + 25));
118  reassert_interrupts(d);
119 }
120 
121 static void luna88k_interrupt_deassert(struct interrupt *interrupt)
122 {
123  struct luna88k_data *d = (struct luna88k_data *) interrupt->extra;
124  d->interrupt_status[0] &= ~(1 << (interrupt->line + 25));
125  reassert_interrupts(d);
126 }
127 
128 
129 static void reassert_serial_interrupt(struct luna88k_data* d)
130 {
131  bool assertSerial = false;
132 
133  if (d->fb != NULL) {
134  /* Workstation keyboard: */
135  if ((d->obio_sio_wr[1][SCC_WR1] & SCC_WR1_RXI_ALL_CHAR) ||
138  assertSerial = true;
139  }
140  } else {
141  /* Serial: */
142  if ((d->obio_sio_wr[0][SCC_WR1] & SCC_WR1_RXI_ALL_CHAR) ||
145  assertSerial = true;
146  }
147  }
148 
149  if (d->obio_sio_wr[0][SCC_WR1] & SCC_WR1_TX_IE) {
150  assertSerial = true;
151  }
152 
153  if (d->interrupt_delay > 0) {
154  assertSerial = false;
155  d->interrupt_delay --;
156  }
157 
158  if (assertSerial) {
160  d->interrupt_delay = 130;
161  } else {
163  }
164 }
165 
166 
167 DEVICE_TICK(luna88k)
168 {
169  struct luna88k_data *d = (struct luna88k_data *) extra;
170 
171  /* TODO: Correct timing. */
172  if (d->timer_tick_counter_bogus < 3) {
173  if (++d->timer_tick_counter_bogus >= 3)
175  }
176 
177  /* Serial: */
178  reassert_serial_interrupt(d);
179 }
180 
181 
182 static void swapBitOrder(uint8_t* data, int len)
183 {
184  for (int bo = 0; bo < len; bo ++)
185  {
186  uint8_t b = (uint8_t)data[bo];
187  uint8_t c = 0x00;
188  for (int i = 0; i < 8; i++)
189  {
190  if (b & (128 >> i))
191  c |= (1 << i);
192  }
193 
194  data[bo] = c;
195  }
196 }
197 
198 
200 {
201  struct tm *tmp;
202  time_t timet;
203  uint32_t addr = relative_addr + LUNA88K_REGISTERS_BASE;
204  uint64_t idata = 0, odata = 0;
205  struct luna88k_data *d = (struct luna88k_data *) extra;
206  int cpunr;
207  int sio_devnr;
208 
209  if (writeflag == MEM_WRITE)
210  idata = memory_readmax64(cpu, data, len);
211 
212  if (addr >= FUSE_ROM_ADDR && len == sizeof(uint32_t) &&
214  if (writeflag == MEM_READ) {
215  odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
216  memory_writemax64(cpu, data, len, odata);
217  } else {
218  d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)] = idata;
219  }
220  return 1;
221  }
222 
223  if (addr >= FUSE_ROM_ADDR && len == sizeof(uint8_t) &&
225  if (writeflag == MEM_READ) {
226  odata = d->fuse_rom[(addr - FUSE_ROM_ADDR) / sizeof(uint32_t)];
227  odata >>= ((3 - (addr & 3)) * 8);
228  memory_writemax64(cpu, data, len, odata);
229  } else {
230  fatal("TODO: luna88k byte write to fuse\n");
231  }
232  return 1;
233  }
234 
235  if (addr >= NVRAM_ADDR && addr + len <= NVRAM_ADDR + NVRAM_SPACE) {
236  size_t offset = addr - NVRAM_ADDR;
237  if (writeflag == MEM_READ) {
238  memmove(data, d->nvram + offset, len);
239  } else {
240  memmove(d->nvram + offset, data, len);
241  }
242  return 1;
243  }
244 
245  if (addr >= NVRAM_ADDR_88K2 && addr < NVRAM_ADDR_88K2 + NVRAM_SPACE && len == sizeof(uint8_t)) {
246  if (writeflag == MEM_READ) {
247  odata = d->nvram[addr - NVRAM_ADDR_88K2];
248  memory_writemax64(cpu, data, len, odata);
249  } else {
250  d->nvram[addr - NVRAM_ADDR_88K2] = idata;
251  }
252  return 1;
253  }
254 
255  if (addr >= BMAP_BMP && addr < BMAP_BMP + 0x40000) {
256  // X resolution is 1280, but stride is 2048.
257  uint32_t s = 2048 * 1024 / 8;
258  addr -= (uint64_t)(uint32_t)(BMAP_BMP);
259  swapBitOrder(data, len);
260  if (addr + len - 1 < s) {
261  if (addr >= 8)
262  addr -= 8;
263  dev_fb_access(cpu, cpu->mem, addr, data, len, writeflag, d->fb);
264  swapBitOrder(data, len);
265  return 1;
266  }
267  else
268  return 1;
269  }
270 
271  if (addr >= BMAP_BMAP0 && addr < BMAP_BMAP0 + 0x40000) {
272  // X resolution is 1280, but stride is 2048.
273  uint32_t s = 2048 * 1024 / 8;
274  addr -= (uint64_t)(uint32_t)(BMAP_BMAP0);
275  swapBitOrder(data, len);
276  if (addr + len - 1 < s) {
277  if (addr >= 8)
278  addr -= 8;
279  dev_fb_access(cpu, cpu->mem, addr, data, len, writeflag, d->fb);
280  swapBitOrder(data, len);
281  return 1;
282  }
283  else
284  return 1;
285  }
286 
287  if (addr >= BMAP_PALLET2 && addr < BMAP_PALLET2 + 16) {
288  /* Ignore for now. */
289  return 1;
290  }
291 
293  /* Ignore for now. */
294  return 1;
295  }
296 
297  switch (addr) {
298 
299  case 0x3ffffff0:
300  /* Accessed by OpenBSD/luna88k to trigger an illegal address */
301  cpu->cd.m88k.cmmu[1]->reg[CMMU_PFSR] = CMMU_PFSR_BERROR << 16;
302  break;
303 
304  case PROM_ADDR: /* 0x41000000 */
305  /* OpenBSD/luna88k write here during boot. Ignore for now. (?) */
306  break;
307 
308  case OBIO_CAL_CTL: /* calendar control register */
309  break;
310  case OBIO_CAL_SEC:
311  timet = time(NULL); tmp = gmtime(&timet);
312  odata = BCD(tmp->tm_sec) << 24;
313  break;
314  case OBIO_CAL_MIN:
315  timet = time(NULL); tmp = gmtime(&timet);
316  odata = BCD(tmp->tm_min) << 24;
317  break;
318  case OBIO_CAL_HOUR:
319  timet = time(NULL); tmp = gmtime(&timet);
320  odata = BCD(tmp->tm_hour) << 24;
321  break;
322  case OBIO_CAL_DOW:
323  timet = time(NULL); tmp = gmtime(&timet);
324  odata = BCD(tmp->tm_wday + 0) << 24;
325  break;
326  case OBIO_CAL_DAY:
327  timet = time(NULL); tmp = gmtime(&timet);
328  odata = BCD(tmp->tm_mday) << 24;
329  break;
330  case OBIO_CAL_MON:
331  timet = time(NULL); tmp = gmtime(&timet);
332  odata = BCD(tmp->tm_mon + 1) << 24;
333  break;
334  case OBIO_CAL_YEAR:
335  timet = time(NULL); tmp = gmtime(&timet);
336  odata = BCD(tmp->tm_year - 2000) << 24; // ?
337  break;
338 
339  case OBIO_PIO0A: /* 0x49000000: PIO-0 port A */
340  /* OpenBSD reads dipswitch settings from PIO0A and B. */
341  odata = 0; // high byte
342  if (cpu->machine->x11_md.in_use)
343  odata |= 0x40;
344  odata |= 0x80; // multi-user mode
345  odata |= 0x20; // don't ask name
346  odata |= 0x10; // don't do manual UKC config
347  break;
348 
349  case OBIO_PIO0B: /* 0x49000004: PIO-0 port B */
350  /* OpenBSD reads dipswitch settings from PIO0A and B. */
351  odata = 0x00; // low byte
352  break;
353 
354  case OBIO_PIO0: /* 0x4900000C: PIO-0 control */
355  /* TODO: Implement for real. */
356  break;
357 
358  case OBIO_PIO1A: /* 0x4d000000: PIO-0 port A */
359  case OBIO_PIO1B: /* 0x4d000004: PIO-0 port B */
360  case OBIO_PIO1: /* 0x4d00000C: PIO-0 control */
361  /* Ignore for now. (?) */
362  break;
363 
364  case OBIO_SIO + 0: /* 0x51000000: data channel 0 */
365  case OBIO_SIO + 4: /* 0x51000004: cmd channel 0 */
366  case OBIO_SIO + 8: /* 0x51000008: data channel 1 */
367  case OBIO_SIO + 0xc: /* 0x5100000c: cmd channel 1 */
368  sio_devnr = ((addr - OBIO_SIO) / 8) & 1;
369 
370  if ((addr - OBIO_SIO) & 4) {
371  /* cmd */
372 
373  /* Similar to dev_scc.cc ? */
374  if (writeflag == MEM_WRITE) {
375  if (d->obio_sio_regno[sio_devnr] == 0) {
376  int regnr = idata & 7;
377 
378  d->obio_sio_regno[sio_devnr] = regnr;
379 
380  // printf("[ sio: setting regno for next operation to 0x%02x ]\n", (int)regnr);
381 
382  /* High bits are command. */
383  } else {
384  int regnr = d->obio_sio_regno[sio_devnr] & 7;
385  d->obio_sio_wr[sio_devnr][regnr] = idata;
386 
387  // printf("[ sio: setting reg 0x%02x = 0x%02x ]\n", d->obio_sio_regno[sio_devnr], (int)idata);
388 
389  d->obio_sio_regno[sio_devnr] = 0;
390 
391  reassert_serial_interrupt(d);
392  }
393  } else {
395 
397  ( (d->fb == NULL && sio_devnr == 0) ||
398  (d->fb != NULL && sio_devnr == 1)) )
399  d->obio_sio_rr[sio_devnr][SCC_RR0] |= SCC_RR0_RX_AVAIL;
400 
401  d->obio_sio_rr[sio_devnr][SCC_RR1] = SCC_RR1_ALL_SENT;
402 
403  int regnr = d->obio_sio_regno[sio_devnr] & 7;
404  odata = d->obio_sio_rr[sio_devnr][regnr];
405  // printf("[ sio: reading reg 0x%02x: 0x%02x ]\n", regnr, (int)odata);
406  d->obio_sio_regno[sio_devnr] = 0;
407  }
408  } else {
409  /* data */
410  if (writeflag == MEM_WRITE) {
411  if (sio_devnr == 0) {
413  } else
414  fatal("[ luna88k sio dev1 write data: TODO ]\n");
415  } else {
416  if (sio_devnr == 0) {
417  if (d->fb == NULL && console_charavail(d->console_handle)) {
418  odata = console_readchar(d->console_handle);
419  }
420  } else {
421  fatal("[ luna88k sio dev1 read data: TODO ]\n");
422  }
423  }
424 
426  }
427 
428  break;
429 
430  case OBIO_CLOCK0: /* 0x63000000: Clock ack? */
433  break;
434 
435  case INT_ST_MASK0: /* 0x65000000: Interrupt status CPU 0. */
436  case INT_ST_MASK1: /* 0x65000004: Interrupt status CPU 1. */
437  case INT_ST_MASK2: /* 0x65000008: Interrupt status CPU 2. */
438  case INT_ST_MASK3: /* 0x6500000c: Interrupt status CPU 3. */
439  /*
440  * From OpenBSD/luna88k machdep.c source code:
441  *
442  * On write: Bits 31..26 are used to enable/disable levels 6..1.
443  * On read: Bits 31..29 show value 0-7 of current interrupt.
444  * Bits 23..18 show current mask.
445  */
446  cpunr = (addr - INT_ST_MASK0) / 4;
447  if (writeflag == MEM_WRITE) {
448  if ((idata & 0x03ffffff) != 0x00000000) {
449  fatal("[ TODO: luna88k interrupts, idata = 0x%08x, what to do with low bits? ]\n", (uint32_t)idata);
450  exit(1);
451  }
452 
453  d->interrupt_enable[cpunr] = idata;
454  reassert_interrupts(d);
455  } else {
456  uint32_t currentMask = d->interrupt_enable[cpunr];
457  int highestCurrentStatus = 0;
458  odata = currentMask >> 8;
459 
460  for (int i = 1; i <= 6; ++i) {
461  int m = 1 << (25 + i);
462  if (d->interrupt_status[cpunr] & m)
463  highestCurrentStatus = i;
464  }
465 
466  odata |= (highestCurrentStatus << 29);
467  // printf("highest = %i 0x%08x\n", highestCurrentStatus, (int)odata);
468  }
469 
470  break;
471 
472  case SOFT_INT0: /* 0x69000000: Software Interrupt status CPU 0. */
473  case SOFT_INT1: /* 0x69000004: Software Interrupt status CPU 1. */
474  case SOFT_INT2: /* 0x69000008: Software Interrupt status CPU 2. */
475  case SOFT_INT3: /* 0x6900000c: Software Interrupt status CPU 3. */
476  cpunr = (addr - SOFT_INT0) / 4;
477  odata = d->software_interrupt_status[cpunr];
478 
479  // Reading status clears it.
480  d->software_interrupt_status[cpunr] = 0;
481 
482  if (writeflag == MEM_WRITE) {
483  fatal("TODO: luna88k write to software interrupts\n");
484  exit(1);
485  }
486  break;
487 
488  case RESET_CPU_ALL: /* 0x6d000010: Reset all CPUs */
489  cpu->running = 0;
490  break;
491 
492  case BMAP_RFCNT: /* 0xb1000000: RFCNT register */
493  /* video h-origin/v-origin, according to OpenBSD */
494  /* Ignore for now. (?) */
495  break;
496 
497  case BMAP_BMSEL: /* 0xb1000000: BMSEL register */
498  /* Ignore for now. (?) */
499  break;
500 
501  case BMAP_BMAP1: /* 0xb1100000: Bitmap plane 1 */
502  odata = 0xc0dec0de;
503  /* Return dummy value. OpenBSD writes and reads to detect presence
504  of bitplanes. */
505  break;
506 
507  case BMAP_FN + 4 * ROP_THROUGH: /* 0xb12c0014: "common bitmap function" */
508  /* Function 5 is "ROP copy", according to OpenBSD sources. */
509  /* See hitachi_hm53462_rop.h */
510  if (writeflag == MEM_READ) {
511  fatal("[ TODO: luna88k READ from BMAP_FN ROP register? ]\n");
512  cpu->running = 0;
513  return 0;
514  }
515  if (idata != 0xffffffff) {
516  fatal("[ TODO: luna88k write which does not set ALL bits? ]\n");
517  cpu->running = 0;
518  return 0;
519  }
520  break;
521 
522  case SCSI_ADDR + 0x00: /* 0xe1000000: SCSI .. */
523  case SCSI_ADDR + 0x04: /* 0xe1000004: SCSI .. */
524  case SCSI_ADDR + 0x08: /* 0xe1000008: SCSI .. */
525  case SCSI_ADDR + 0x0C: /* 0xe100000C: SCSI .. */
526  case SCSI_ADDR + 0x20: /* 0xe1000020: SCSI .. */
527  case SCSI_ADDR + 0x2c: /* 0xe100002c: SCSI .. */
528  case SCSI_ADDR + 0x30: /* 0xe1000030: SCSI .. */
529  case SCSI_ADDR + 0x34: /* 0xe1000034: SCSI .. */
530  case SCSI_ADDR + 0x38: /* 0xe1000038: SCSI .. */
531  case SCSI_ADDR + 0x40: /* 0xe1000040: SCSI .. */
532  case SCSI_ADDR + 0x44: /* 0xe1000044: SCSI .. */
533  case SCSI_ADDR + 0x48: /* 0xe1000048: SCSI .. */
534  case SCSI_ADDR + 0x4c: /* 0xe100004c: SCSI .. */
535  case SCSI_ADDR + 0x50: /* 0xe1000050: SCSI .. */
536  case SCSI_ADDR + 0x60: /* 0xe1000060: SCSI .. */
537  case SCSI_ADDR + 0x6c: /* 0xe100006c: SCSI .. */
538  case SCSI_ADDR + 0x70: /* 0xe1000070: SCSI .. */
539  case SCSI_ADDR + 0x74: /* 0xe1000074: SCSI .. */
540  case SCSI_ADDR + 0x78: /* 0xe1000078: SCSI .. */
541  /* MB89352 SCSI Protocol Controller */
542  /* Ignore for now. (?) */
543  break;
544 
545  case SCSI_ADDR + 0x10: /* 0xe1000010: SCSI INTS */
546  odata = 0xffffffff;
547  break;
548 
549  case 0xf1000000: /* Lance Ethernet. TODO. */
550  case 0xf1000004:
551  case 0xf1000008:
552  break;
553 
554  default:fatal("[ luna88k: unimplemented %s address 0x%x",
555  writeflag == MEM_WRITE? "write to" : "read from",
556  (int) addr);
557  if (writeflag == MEM_WRITE)
558  fatal(": 0x%x", (int)idata);
559  fatal(" (%i bits) ]\n", len * 8);
560  exit(1);
561  }
562 
563  if (writeflag == MEM_READ)
564  memory_writemax64(cpu, data, len, odata);
565 
566  return 1;
567 }
568 
569 
570 void add_cmmu_for_cpu(struct devinit* devinit, int cpunr, uint32_t iaddr, uint32_t daddr)
571 {
572  char tmpstr[300];
573  struct m8820x_cmmu *cmmu;
574 
575  /* Instruction CMMU: */
576  CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
577  memset(cmmu, 0, sizeof(struct m8820x_cmmu));
578 
579  if (cpunr < devinit->machine->ncpus)
580  devinit->machine->cpus[cpunr]->cd.m88k.cmmu[0] = cmmu;
581 
582  /* This is a 88200, revision 9: */
583  cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
584  snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=0", iaddr);
585  device_add(devinit->machine, tmpstr);
586 
587  /* ... and data CMMU: */
588  CHECK_ALLOCATION(cmmu = (struct m8820x_cmmu *) malloc(sizeof(struct m8820x_cmmu)));
589  memset(cmmu, 0, sizeof(struct m8820x_cmmu));
590 
591  if (cpunr < devinit->machine->ncpus)
592  devinit->machine->cpus[cpunr]->cd.m88k.cmmu[1] = cmmu;
593 
594  /* This is also a 88200, revision 9: */
595  cmmu->reg[CMMU_IDR] = (M88200_ID << 21) | (9 << 16);
596  cmmu->batc[8] = BATC8;
597  cmmu->batc[9] = BATC9;
598  snprintf(tmpstr, sizeof(tmpstr), "m8820x addr=0x%x addr2=1", daddr);
599  device_add(devinit->machine, tmpstr);
600 }
601 
602 
603 DEVINIT(luna88k)
604 {
605  char n[100];
606  struct luna88k_data *d;
607 
608  CHECK_ALLOCATION(d = (struct luna88k_data *) malloc(sizeof(struct luna88k_data)));
609  memset(d, 0, sizeof(struct luna88k_data));
610 
611 
613  LUNA88K_REGISTERS_BASE, LUNA88K_REGISTERS_LENGTH, dev_luna88k_access, (void *)d,
614  DM_DEFAULT, NULL);
615 
616  /*
617  * Connect to the CPU's interrupt pin, and register
618  * 6 hardware interrupts:
619  */
621  for (int i = 1; i <= 6; i++) {
622  struct interrupt templ;
623  snprintf(n, sizeof(n), "%s.luna88k.%i", devinit->interrupt_path, i);
624 
625  memset(&templ, 0, sizeof(templ));
626  templ.line = i;
627  templ.name = n;
628  templ.extra = d;
629  templ.interrupt_assert = luna88k_interrupt_assert;
630  templ.interrupt_deassert = luna88k_interrupt_deassert;
631 
632  // debug("registering irq: %s\n", n);
633 
635  }
636 
637  /* Timer. */
638  snprintf(n, sizeof(n), "%s.luna88k.6", devinit->interrupt_path);
639  INTERRUPT_CONNECT(n, d->timer_irq);
641  dev_luna88k_tick, d, TICK_STEPS_SHIFT);
642 
643  /* IRQ 5,4,3 (?): "autovec" according to OpenBSD */
644  snprintf(n, sizeof(n), "%s.luna88k.5", devinit->interrupt_path);
645  INTERRUPT_CONNECT(n, d->irqX);
646 
647  d->console_handle = console_start_slave(devinit->machine, "SIO", 1);
648 
650  {
652  0x100000000ULL + BMAP_BMAP0, VFB_GENERIC,
653  1280, 1024, 2048, 1024, 1, "LUNA 88K");
654  }
655 
656  if (devinit->machine->ncpus > 4)
657  {
658  printf("LUNA 88K can't have more than 4 CPUs.\n");
659  exit(1);
660  }
661 
666 
667  return 1;
668 }
669 
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