38 int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page) \
39 / sizeof(struct sh_instr_call); \
40 cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) \
41 << SH_INSTR_ALIGNMENT_SHIFT); \
42 cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT); \
45 #define ABORT_EXECUTION { SYNCH_PC; \
46 fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \
47 cpu->cd.sh.next_ic = ¬hing_call; \
49 debugger_n_steps_left_before_interaction = 0; }
51 #define RES_INST_IF_NOT_MD \
52 if (!(cpu->cd.sh.sr & SH_SR_MD)) { \
54 sh_exception(cpu, EXPEVT_RES_INST, 0, 0); \
58 #define FLOATING_POINT_AVAILABLE_CHECK \
59 if (cpu->cd.sh.sr & SH_SR_FD) { \
62 if (cpu->delay_slot) \
63 sh_exception(cpu, EXPEVT_FPU_SLOT_DISABLE, 0, 0);\
65 sh_exception(cpu, EXPEVT_FPU_DISABLE, 0, 0); \
159 res -= (uint64_t)
reg(
ic->arg[0]);
166 reg(
ic->arg[1]) = (uint32_t) res;
170 uint32_t r =
reg(
ic->arg[0]);
171 reg(
ic->arg[1]) = (r & 0xffff0000) | ((r >> 8)&0xff) | ((r&0xff) << 8);
175 uint32_t r =
reg(
ic->arg[0]);
176 reg(
ic->arg[1]) = (r >> 16) | (r << 16);
217 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
220 p[
addr & 0xfff] ^=
ic->arg[0];
240 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
243 p[
addr & 0xfff] |=
ic->arg[0];
263 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
266 p[
addr & 0xfff] &=
ic->arg[0];
310 X(mov_b_rm_predec_rn)
312 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint8_t);
313 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
329 X(mov_w_rm_predec_rn)
331 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint16_t);
332 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
354 X(mov_l_rm_predec_rn)
356 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint32_t);
357 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
379 X(stc_l_rm_predec_rn_md)
381 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint32_t);
382 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
419 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
463 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
514 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
532 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
554 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
577 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
588 size_t r1 =
ic->arg[1];
589 int ofs = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
591 fatal(
"ODD fmov_rm_frn: TODO");
632 reg(
ic->arg[1] + 4) = data2;
638 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
643 fatal(
"fmov_r0_rm_frn: sz=1 (register pair): TODO\n");
666 X(fmov_rm_postinc_frn)
670 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
671 size_t r1 =
ic->arg[1];
675 int ofs = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
714 reg(
ic->arg[0]) =
addr +
sizeof(uint32_t);
719 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
736 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
757 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
775 X(mov_b_arg1_postinc_to_arg0)
778 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
794 X(mov_w_arg1_postinc_to_arg0)
797 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
818 X(mov_l_arg1_postinc_to_arg0)
821 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
842 X(mov_l_arg1_postinc_to_arg0_md)
845 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
873 X(mov_l_arg1_postinc_to_arg0_fp)
876 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
907 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
926 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
949 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
972 ((
ic->arg[0] >> 4) << 2);
973 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
996 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
1015 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
1058 X(mov_b_store_rm_rn)
1061 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1075 X(mov_w_store_rm_rn)
1078 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1097 X(mov_l_store_rm_rn)
1100 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1122 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1132 size_t r0 =
ic->arg[1];
1133 int ofs = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
1135 fatal(
"ODD fmov_frm_rn: TODO");
1140 uint32_t data2 =
reg(
ic->arg[0] + 4);
1171 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1177 fatal(
"fmov_frm_r0_rn: sz=1 (register pair): TODO\n");
1198 X(fmov_frm_predec_rn)
1202 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1203 size_t r0 =
ic->arg[0];
1207 int ofs0 = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
1250 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1266 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1288 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1307 X(mov_b_r0_disp_gbr)
1310 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1323 X(mov_w_r0_disp_gbr)
1326 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1345 X(mov_l_r0_disp_gbr)
1348 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1370 ((
ic->arg[1] >> 4) << 2);
1371 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1393 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1410 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[
addr >> 12];
1449 uint64_t res =
reg(
ic->arg[1]);
1450 res += (uint64_t)
reg(
ic->arg[0]);
1453 if ((res >> 32) & 1)
1457 reg(
ic->arg[1]) = (uint32_t) res;
1465 uint64_t res =
reg(
ic->arg[1]);
1466 res -= (uint64_t)
reg(
ic->arg[0]);
1469 if ((res >> 32) & 1)
1473 reg(
ic->arg[1]) = (uint32_t) res;
1484 if (
reg(
ic->arg[0]))
1491 uint32_t rn =
reg(
ic->arg[1]), rm =
reg(
ic->arg[0]);
1492 reg(
ic->arg[1]) = (rn >> 16) | (rm << 16);
1510 int q =
reg(
ic->arg[1]) & 0x80000000;
1511 int m =
reg(
ic->arg[0]) & 0x80000000;
1526 uint32_t op1 =
reg(
ic->arg[0]), op2 =
reg(
ic->arg[1]);
1530 op2_64 = (uint32_t) ((op2 << 1) +
t);
1532 op2_64 -= (uint64_t)op1;
1534 op2_64 += (uint64_t)op1;
1535 q ^= m ^ ((op2_64 >> 32) & 1);
1542 reg(
ic->arg[1]) = (uint32_t) op2_64;
1563 (int32_t)(int16_t)
reg(
ic->arg[1]);
1568 (int32_t)(uint16_t)
reg(
ic->arg[1]);
1572 uint64_t rm = (int32_t)
reg(
ic->arg[0]), rn = (int32_t)
reg(
ic->arg[1]);
1573 uint64_t res = rm * rn;
1579 uint64_t rm =
reg(
ic->arg[0]), rn =
reg(
ic->arg[1]), res;
1623 if ((int32_t)
reg(
ic->arg[1]) >= (int32_t)
reg(
ic->arg[0]))
1637 if ((int32_t)
reg(
ic->arg[1]) > (int32_t)
reg(
ic->arg[0]))
1644 if ((int32_t)
reg(
ic->arg[1]) >= 0)
1651 if ((int32_t)
reg(
ic->arg[1]) > 0)
1658 uint32_t r0 =
reg(
ic->arg[0]), r1 =
reg(
ic->arg[1]);
1660 if ((r0 & 0xff000000) == (r1 & 0xff000000))
1662 else if ((r0 & 0xff0000) == (r1 & 0xff0000))
1664 else if ((r0 & 0xff00) == (r1 & 0xff00))
1666 else if ((r0 & 0xff) == (r1 & 0xff))
1691 uint32_t rn =
reg(
ic->arg[1]);
1692 if (rn & 0x80000000)
1696 reg(
ic->arg[1]) = rn << 1;
1700 uint32_t rn =
reg(
ic->arg[1]);
1705 reg(
ic->arg[1]) = rn >> 1;
1709 uint32_t rn =
reg(
ic->arg[1]), x;
1710 if (rn & 0x80000000) {
1717 reg(
ic->arg[1]) = (rn << 1) | x;
1721 uint32_t rn =
reg(
ic->arg[1]);
1726 reg(
ic->arg[1]) = (rn >> 1) | (rn << 31);
1730 int32_t rn =
reg(
ic->arg[1]);
1735 reg(
ic->arg[1]) = rn >> 1;
1739 uint32_t rn =
reg(
ic->arg[1]), top;
1740 top = rn & 0x80000000;
1748 reg(
ic->arg[1]) = rn;
1752 uint32_t rn =
reg(
ic->arg[1]), bottom;
1761 reg(
ic->arg[1]) = rn;
1765 uint32_t rn =
reg(
ic->arg[1]) - 1;
1770 reg(
ic->arg[1]) = rn;
1789 int32_t rn =
reg(
ic->arg[1]);
1790 int32_t rm =
reg(
ic->arg[0]);
1802 reg(
ic->arg[1]) = rn;
1806 uint32_t rn =
reg(
ic->arg[1]);
1807 int32_t rm =
reg(
ic->arg[0]);
1817 reg(
ic->arg[1]) = rn;
1835 target +=
ic->arg[0];
1852 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[0];
1862 target +=
ic->arg[0];
1881 target +=
ic->arg[0];
1904 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[0];
1912 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1930 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1949 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1994 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[1];
1999 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[1];
2006 target +=
ic->arg[0];
2025 target +=
ic->arg[0];
2049 (
struct sh_instr_call *)
ic->arg[1];
2065 (
struct sh_instr_call *)
ic->arg[1];
2203 uint32_t old_hi, old_lo;
2235 X(copy_privileged_register)
2261 cpu->
cd.
sh.next_ic = ¬hing_call;
2325 r0 =
ic->arg[0]; r1 =
ic->arg[1];
2326 ofs0 = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2327 ofs1 = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2334 reg(r1 + 4) =
reg(r0 + 4);
2352 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2353 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2357 reg(
ic->arg[0]) = (uint32_t) ieee;
2375 int64_t r1 = ((uint64_t)
reg(
ic->arg[0]) << 32) +
2376 reg(
ic->arg[0] +
sizeof(uint32_t));
2405 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2406 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2415 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2416 ((uint64_t)
reg(
ic->arg[0]) << 32);
2436 double fpulAngle = ((double)
cpu->
cd.
sh.
fpul) * 2.0 * M_PI / 65536.0;
2441 reg(
ic->arg[0] +
sizeof(uint32_t)) =
2472 frm0.
f * frn0.
f + frm1.
f * frn1.
f +
2473 frm2.
f * frn2.
f + frm3.
f * frn3.
f;
2488 double frnp0 = 0.0, frnp1 = 0.0, frnp2 = 0.0, frnp3 = 0.0;
2498 for (i=0; i<16; i++)
2503 frnp0 += xmtrx[i*4].
f * frn[i].
f;
2506 frnp1 += xmtrx[i*4 + 1].
f * frn[i].
f;
2509 frnp2 += xmtrx[i*4 + 2].
f * frn[i].
f;
2512 frnp3 += xmtrx[i*4 + 3].
f * frn[i].
f;
2543 int ofs0 = (
ic->arg[0] - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2545 fatal(
"TODO: fneg_frn odd register in double prec. mode.\n");
2551 reg(
ic->arg[0]) ^= 0x80000000;
2560 int ofs0 = (
ic->arg[0] - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2562 fatal(
"TODO: fneg_frn odd register in double prec. mode.\n");
2568 reg(
ic->arg[0]) &= 0x7fffffff;
2579 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2580 ((uint64_t)
reg(
ic->arg[0]) << 32);
2583 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2584 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2587 int32_t ieee, r1 =
reg(
ic->arg[0]);
2590 reg(
ic->arg[0]) = ieee;
2604 fatal(
"Double-precision fsrra? TODO\n");
2609 int32_t ieee, r1 =
reg(
ic->arg[0]);
2612 reg(
ic->arg[0]) = ieee;
2637 int64_t r1, r2, ieee;
2640 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2641 ((uint64_t)
reg(
ic->arg[0]) << 32);
2642 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2643 ((uint64_t)
reg(
ic->arg[1]) << 32);
2647 result = op2.
f + op1.
f;
2649 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2650 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2653 uint32_t r1, r2, ieee;
2656 r1 =
reg(
ic->arg[0]);
2657 r2 =
reg(
ic->arg[1]);
2661 result = op2.
f + op1.
f;
2663 reg(
ic->arg[1]) = (uint32_t) ieee;
2674 int64_t r1, r2, ieee;
2676 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2677 ((uint64_t)
reg(
ic->arg[0]) << 32);
2678 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2679 ((uint64_t)
reg(
ic->arg[1]) << 32);
2682 result = op2.
f - op1.
f;
2684 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2685 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2688 uint32_t r1, r2, ieee;
2690 r1 =
reg(
ic->arg[0]);
2691 r2 =
reg(
ic->arg[1]);
2694 result = op2.
f - op1.
f;
2696 reg(
ic->arg[1]) = (uint32_t) ieee;
2707 int64_t r1, r2, ieee;
2710 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2711 ((uint64_t)
reg(
ic->arg[0]) << 32);
2712 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2713 ((uint64_t)
reg(
ic->arg[1]) << 32);
2717 result = op2.
f * op1.
f;
2719 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2720 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2723 uint32_t r1, r2, ieee;
2726 r1 =
reg(
ic->arg[0]);
2727 r2 =
reg(
ic->arg[1]);
2731 result = op2.
f * op1.
f;
2733 reg(
ic->arg[1]) = (uint32_t) ieee;
2744 int64_t r1, r2, ieee;
2747 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2748 ((uint64_t)
reg(
ic->arg[0]) << 32);
2749 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2750 ((uint64_t)
reg(
ic->arg[1]) << 32);
2755 result = op2.
f / op1.
f;
2761 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2762 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2765 uint32_t r1, r2, ieee;
2768 r1 =
reg(
ic->arg[0]);
2769 r2 =
reg(
ic->arg[1]);
2774 result = op2.
f / op1.
f;
2780 reg(
ic->arg[1]) = (uint32_t) ieee;
2786 int32_t r1, r2, fr0 =
cpu->
cd.
sh.
fr[0], ieee;
2795 reg(
ic->arg[1]) = ieee;
2806 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2807 ((uint64_t)
reg(
ic->arg[0]) << 32);
2808 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2809 ((uint64_t)
reg(
ic->arg[1]) << 32);
2814 uint32_t r1 =
reg(
ic->arg[0]), r2 =
reg(
ic->arg[1]);
2833 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2834 ((uint64_t)
reg(
ic->arg[0]) << 32);
2835 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2836 ((uint64_t)
reg(
ic->arg[1]) << 32);
2841 uint32_t r1 =
reg(
ic->arg[0]), r2 =
reg(
ic->arg[1]);
2879 uint32_t
addr =
reg(
ic->arg[1]), extaddr;
2882 if (addr < 0xe0000000U || addr >= 0xe4000000U)
2891 extaddr =
addr & 0x03ffffe0;
2892 sq_nr =
addr & 0x20? 1 : 0;
2917 fatal(
"Store Queue to external memory, when "
2918 "MMU enabled: Not yet implemented... TODO\n");
2923 for (ofs = 0; ofs < 32; ofs +=
sizeof(uint32_t)) {
2926 + sq_nr * 0x20, (
unsigned char *)
2943 uint8_t byte, newbyte;
2953 newbyte =
byte | 0x80;
2985 fatal(
"SH prom_emul: unimplemented machine type.\n");
2991 cpu->
cd.
sh.next_ic = ¬hing_call;
2992 }
else if ((uint32_t)
cpu->
pc != old_pc) {
3013 X(bt_samepage_wait_for_variable)
3023 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[
addr >> 12];
3029 uint32_t
data = p[(
addr & 0xfff) >> 2];
3073 if (
ic[-2].
f ==
instr(mov_l_disp_gbr_r0) &&
3074 ic[-1].f ==
instr(cmpeq_rm_rn) &&
3075 (
ic[-1].arg[0] == (size_t) &
cpu->
cd.
sh.
r[0] ||
3076 ic[-1].arg[1] == (
size_t) &
cpu->
cd.
sh.
r[0]) &&
3077 ic[0].arg[1] == (
size_t) &
ic[-2]) {
3078 ic[-2].f =
instr(bt_samepage_wait_for_variable);
3138 int low_pc = ((size_t)
ic - (
size_t)
cpu->
cd.
sh.cur_ic_page)
3139 /
sizeof(
struct sh_instr_call);
3152 fatal(
"end_of_page2: fatal error, we're in a delay slot\n");
3170 uint32_t
addr, low_pc, iword;
3171 unsigned char *
page;
3172 unsigned char ib[2];
3173 int main_opcode, isize =
sizeof(ib);
3174 int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
3175 void (*samepage_function)(
struct cpu *,
struct sh_instr_call *);
3178 low_pc = ((size_t)
ic - (
size_t)
cpu->
cd.
sh.cur_ic_page)
3179 /
sizeof(
struct sh_instr_call);
3185 in_crosspage_delayslot = 1;
3199 memcpy(ib,
page + (
addr & 0xfff), isize);
3204 fatal(
"to_be_translated(): read failed: TODO\n");
3210 uint16_t *p = (uint16_t *) ib;
3219 main_opcode = iword >> 12;
3220 r8 = (iword >> 8) & 0xf;
3221 r4 = (iword >> 4) & 0xf;
3226 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
3228 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
3239 switch (main_opcode) {
3244 ic->f =
instr(mov_b_rm_r0_rn);
3245 }
else if (lo4 == 0x5) {
3247 ic->f =
instr(mov_w_rm_r0_rn);
3248 }
else if (lo4 == 0x6) {
3250 ic->f =
instr(mov_l_rm_r0_rn);
3251 }
else if (lo4 == 0x7) {
3254 }
else if (iword == 0x000b) {
3259 }
else if (lo4 == 0xc) {
3261 ic->f =
instr(mov_b_r0_rm_rn);
3262 }
else if (lo4 == 0xd) {
3264 ic->f =
instr(mov_w_r0_rm_rn);
3265 }
else if (lo4 == 0xe) {
3267 ic->f =
instr(mov_l_r0_rm_rn);
3268 }
else if (iword == 0x0008) {
3271 }
else if (iword == 0x0018) {
3274 }
else if (iword == 0x0019) {
3277 }
else if (iword == 0x001b) {
3280 }
else if (iword == 0x0028) {
3283 }
else if (iword == 0x002b) {
3286 }
else if (iword == 0x0038) {
3289 }
else if (iword == 0x0048) {
3292 }
else if (iword == 0x0058) {
3295 }
else if ((lo8 & 0x8f) == 0x82) {
3297 ic->f =
instr(copy_privileged_register);
3305 ic->f =
instr(copy_privileged_register);
3314 ic->arg[0] = (int32_t) (
addr &
3321 if (iword & 0x0f00) {
3323 fatal(
"Unimplemented NOP"
3341 ic->f =
instr(copy_privileged_register);
3346 ic->arg[0] = (int32_t) (
addr &
3359 ic->f =
instr(copy_privileged_register);
3363 ic->f =
instr(copy_privileged_register);
3367 ic->f =
instr(copy_fp_register);
3372 ic->f =
instr(copy_fp_register);
3400 ic->f =
instr(copy_privileged_register);
3405 fatal(
"Unimplemented opcode 0x%x,"
3406 "0x%03x\n", main_opcode,
3414 ic->f =
instr(mov_l_rm_disp_rn);
3415 ic->arg[1] = r8 + (lo4 << 4);
3421 ic->f =
instr(mov_b_store_rm_rn);
3424 ic->f =
instr(mov_w_store_rm_rn);
3427 ic->f =
instr(mov_l_store_rm_rn);
3430 ic->f =
instr(mov_b_rm_predec_rn);
3433 ic->f =
instr(mov_w_rm_predec_rn);
3436 ic->f =
instr(mov_l_rm_predec_rn);
3468 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3513 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3522 }
else if (lo4 == 0xd) {
3524 }
else if ((lo8 & 0x8f) == 0x83) {
3526 ic->f =
instr(stc_l_rm_predec_rn_md);
3529 }
else if ((lo8 & 0x8f) == 0x87) {
3531 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3533 }
else if ((lo8 & 0x8f) == 0x8e) {
3535 ic->f =
instr(copy_privileged_register);
3547 ic->f =
instr(mov_l_rm_predec_rn);
3551 ic->f =
instr(stc_l_rm_predec_rn_md);
3561 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3565 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3585 ic->arg[1] = (
addr & 0xffe) + 4;
3597 ic->f =
instr(mov_l_rm_predec_rn);
3601 ic->f =
instr(mov_l_rm_predec_rn);
3608 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3612 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3641 ic->f =
instr(mov_l_rm_predec_rn);
3646 ic->f =
instr(stc_l_rm_predec_rn_md);
3656 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3660 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3680 ic->arg[1] = (
addr & 0xffe) + 4;
3683 ic->f =
instr(copy_privileged_register);
3688 ic->f =
instr(stc_l_rm_predec_rn_md);
3692 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3696 ic->f =
instr(copy_privileged_register);
3701 ic->f =
instr(stc_l_rm_predec_rn_md);
3705 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3709 ic->f =
instr(copy_privileged_register);
3714 ic->f =
instr(mov_l_rm_predec_rn);
3719 ic->f =
instr(mov_l_arg1_postinc_to_arg0_fp);
3723 ic->f =
instr(copy_fp_register);
3728 ic->f =
instr(mov_l_rm_predec_rn);
3735 ic->f =
instr(mov_l_arg1_postinc_to_arg0_fp);
3743 ic->f =
instr(copy_privileged_register);
3748 fatal(
"Unimplemented opcode 0x%x,"
3749 "0x%02x\n", main_opcode, lo8);
3756 ic->f =
instr(mov_l_disp_rm_rn);
3757 ic->arg[0] = r4 + (lo4 << 4);
3775 ic->f =
instr(mov_b_arg1_postinc_to_arg0);
3781 ic->f =
instr(mov_w_arg1_postinc_to_arg0);
3787 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3824 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3832 ic->arg[0] = (int8_t)lo8;
3846 ic->arg[0] = (int8_t)lo8 * 2 +
3849 samepage_function = NULL;
3853 ic->f =
instr(mov_b_r0_disp_rn);
3858 ic->f =
instr(mov_w_r0_disp_rn);
3860 ic->arg[1] = lo4 * 2;
3863 ic->f =
instr(mov_b_disp_rn_r0);
3868 ic->f =
instr(mov_w_disp_rn_r0);
3870 ic->arg[1] = lo4 * 2;
3874 ic->arg[0] = (int8_t)lo8;
3882 samepage_function =
instr(bf_samepage);
3886 samepage_function =
instr(bt_s_samepage);
3890 samepage_function =
instr(bf_s_samepage);
3893 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3899 if (samepage_function != NULL &&
ic->arg[0] < 0x1000 &&
3900 (
addr & 0xfff) < 0xffe) {
3901 ic->arg[1] = (size_t) (
cpu->
cd.
sh.cur_ic_page +
3903 ic->f = samepage_function;
3912 ic->f =
instr(mov_w_disp_pc_rn);
3918 if (
ic->arg[0] < 0x1000 &&
page != NULL) {
3919 uint16_t *p = (uint16_t *)
page;
3920 uint16_t
data = p[
ic->arg[0] >> 1];
3926 ic->arg[0] = (int16_t)
data;
3932 samepage_function = NULL;
3934 switch (main_opcode) {
3937 samepage_function =
instr(bra_samepage);
3945 samepage_function =
instr(bsr_samepage);
3952 (((int32_t)(int16_t)((iword & 0xfff) << 4)) >> 3) );
3955 if (samepage_function != NULL &&
ic->arg[0] < 0x1000 &&
3956 (
addr & 0xfff) < 0xffe) {
3957 ic->arg[0] = (size_t) (
cpu->
cd.
sh.cur_ic_page +
3959 ic->f = samepage_function;
3966 ic->f =
instr(mov_b_r0_disp_gbr);
3970 ic->f =
instr(mov_w_r0_disp_gbr);
3971 ic->arg[1] = lo8 << 1;
3974 ic->f =
instr(mov_l_r0_disp_gbr);
3975 ic->arg[1] = lo8 << 2;
3979 ic->arg[0] = lo8 << 2;
3982 ic->f =
instr(mov_b_disp_gbr_r0);
3986 ic->f =
instr(mov_w_disp_gbr_r0);
3987 ic->arg[1] = lo8 << 1;
3990 ic->f =
instr(mov_l_disp_gbr_r0);
3991 ic->arg[1] = lo8 << 2;
3995 ic->arg[0] = lo8 * 4 + (
addr &
4016 ic->f =
instr(and_b_imm_r0_gbr);
4020 ic->f =
instr(xor_b_imm_r0_gbr);
4024 ic->f =
instr(or_b_imm_r0_gbr);
4028 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
4035 ic->f =
instr(mov_l_disp_pc_rn);
4041 if (
ic->arg[0] < 0x1000 &&
page != NULL) {
4042 uint32_t *p = (uint32_t *)
page;
4043 uint32_t
data = p[
ic->arg[0] >> 2];
4055 ic->arg[0] = (int8_t)lo8;
4067 }
else if (lo4 == 0x1) {
4072 }
else if (lo4 == 0x2) {
4077 }
else if (lo4 == 0x3) {
4082 }
else if (lo4 == 0x4) {
4084 ic->f =
instr(fcmp_eq_frm_frn);
4087 }
else if (lo4 == 0x5) {
4089 ic->f =
instr(fcmp_gt_frm_frn);
4092 }
else if (lo4 == 0x6) {
4094 ic->f =
instr(fmov_r0_rm_frn);
4097 }
else if (lo4 == 0x7) {
4099 ic->f =
instr(fmov_frm_r0_rn);
4102 }
else if (lo4 == 0x8) {
4107 }
else if (lo4 == 0x9) {
4109 ic->f =
instr(fmov_rm_postinc_frn);
4112 }
else if (lo4 == 0xa) {
4117 }
else if (lo4 == 0xb) {
4119 ic->f =
instr(fmov_frm_predec_rn);
4122 }
else if (lo4 == 0xc) {
4127 }
else if (lo8 == 0x0d) {
4129 ic->f =
instr(copy_fp_register);
4132 }
else if (lo8 == 0x1d) {
4134 ic->f =
instr(copy_fp_register);
4137 }
else if (lo8 == 0x2d) {
4139 ic->f =
instr(float_fpul_frn);
4141 }
else if (lo8 == 0x3d) {
4145 }
else if (lo8 == 0x4d) {
4149 }
else if (lo8 == 0x5d) {
4153 }
else if (lo8 == 0x6d) {
4157 }
else if (lo8 == 0x7d) {
4161 }
else if (lo8 == 0x8d) {
4165 ic->arg[1] = 0x00000000;
4166 }
else if (lo8 == 0x9d) {
4170 ic->arg[1] = 0x3f800000;
4171 }
else if ((iword & 0x01ff) == 0x00ad) {
4173 ic->f =
instr(fcnvsd_fpul_drn);
4175 }
else if ((iword & 0x01ff) == 0x00bd) {
4177 ic->f =
instr(fcnvds_drm_fpul);
4179 }
else if (lo8 == 0xed) {
4182 ic->arg[0] = (size_t)&
cpu->
cd.
sh.
fr[(r8<<2) & 0xc];
4184 }
else if ((iword & 0x01ff) == 0x00fd) {
4188 }
else if (iword == 0xf3fd) {
4191 }
else if (iword == 0xfbfd) {
4194 }
else if ((iword & 0xf3ff) == 0xf1fd) {
4196 ic->f =
instr(ftrv_xmtrx_fvn);
4198 }
else if (lo4 == 0xe) {
4200 ic->f =
instr(fmac_fr0_frm_frn);
4205 fatal(
"Unimplemented opcode 0x%x,0x%02x\n",
4212 fatal(
"Unimplemented main opcode 0x%x\n", main_opcode);
4217 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
4219 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL