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Classes | |
struct | mips_cpu_type_def |
struct | mips_tlb |
struct | mips_coproc |
struct | r3000_cache_line |
struct | mips_cpu |
Macros | |
#define | INITIAL_PC 0xffffffffbfc00000ULL |
#define | INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) |
#define | N_MIPS_COPROC_REGS 32 |
#define | N_MIPS_FCRS 32 |
#define | MIPS_FPU_FCIR 0 |
#define | MIPS_FPU_FCCR 25 |
#define | MIPS_FPU_FCSR 31 |
#define | MIPS_FCSR_FCC0_SHIFT 23 |
#define | MIPS_FCSR_FCC1_SHIFT 25 |
#define | N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) |
#define | N_MIPS_COPROCS 4 |
#define | N_MIPS_GPRS 32 /* General purpose registers */ |
#define | N_MIPS_FPRS 32 /* Floating point registers */ |
#define | MIPS_REGISTER_NAMES |
#define | MIPS_GPR_ZERO 0 /* zero */ |
#define | MIPS_GPR_AT 1 /* at */ |
#define | MIPS_GPR_V0 2 /* v0 */ |
#define | MIPS_GPR_V1 3 /* v1 */ |
#define | MIPS_GPR_A0 4 /* a0 */ |
#define | MIPS_GPR_A1 5 /* a1 */ |
#define | MIPS_GPR_A2 6 /* a2 */ |
#define | MIPS_GPR_A3 7 /* a3 */ |
#define | MIPS_GPR_T0 8 /* t0 */ |
#define | MIPS_GPR_T1 9 /* t1 */ |
#define | MIPS_GPR_T2 10 /* t2 */ |
#define | MIPS_GPR_T3 11 /* t3 */ |
#define | MIPS_GPR_T4 12 /* t4 */ |
#define | MIPS_GPR_T5 13 /* t5 */ |
#define | MIPS_GPR_T6 14 /* t6 */ |
#define | MIPS_GPR_T7 15 /* t7 */ |
#define | MIPS_GPR_S0 16 /* s0 */ |
#define | MIPS_GPR_S1 17 /* s1 */ |
#define | MIPS_GPR_S2 18 /* s2 */ |
#define | MIPS_GPR_S3 19 /* s3 */ |
#define | MIPS_GPR_S4 20 /* s4 */ |
#define | MIPS_GPR_S5 21 /* s5 */ |
#define | MIPS_GPR_S6 22 /* s6 */ |
#define | MIPS_GPR_S7 23 /* s7 */ |
#define | MIPS_GPR_T8 24 /* t8 */ |
#define | MIPS_GPR_T9 25 /* t9 */ |
#define | MIPS_GPR_K0 26 /* k0 */ |
#define | MIPS_GPR_K1 27 /* k1 */ |
#define | MIPS_GPR_GP 28 /* gp */ |
#define | MIPS_GPR_SP 29 /* sp */ |
#define | MIPS_GPR_FP 30 /* fp */ |
#define | MIPS_GPR_RA 31 /* ra */ |
#define | N_HI6 64 |
#define | N_SPECIAL 64 |
#define | N_REGIMM 32 |
#define | IMPOSSIBLE_PADDR 0x1212343456566767ULL |
#define | DEFAULT_PCACHE_SIZE 15 /* 32 KB */ |
#define | DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ |
#define | R3000_TAG_VALID 1 |
#define | R3000_TAG_DIRTY 2 |
#define | MIPS_IC_ENTRIES_SHIFT 10 |
#define | MIPS_N_IC_ARGS 3 |
#define | MIPS_INSTR_ALIGNMENT_SHIFT 2 |
#define | MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
#define | MIPS_PC_TO_IC_ENTRY(a) |
#define | MIPS_ADDR_TO_PAGENR(a) |
#define | MIPS_L2N 17 |
#define | MIPS_L3N 18 |
#define | MIPS_MAX_VPH_TLB_ENTRIES 192 |
Functions | |
void | mips_cpu_interrupt_assert (struct interrupt *interrupt) |
void | mips_cpu_interrupt_deassert (struct interrupt *interrupt) |
int | mips_cpu_instruction_has_delayslot (struct cpu *cpu, unsigned char *ib) |
void | mips_cpu_tlbdump (struct machine *m, int x, int rawflag) |
void | mips_cpu_register_match (struct machine *m, char *name, int writeflag, uint64_t *valuep, int *match_register) |
void | mips_cpu_register_dump (struct cpu *cpu, int gprs, int coprocs) |
int | mips_cpu_disassemble_instr (struct cpu *cpu, unsigned char *instr, int running, uint64_t addr) |
void | mips_cpu_exception (struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64) |
int | mips_cpu_run (struct emul *emul, struct machine *machine) |
void | mips_cpu_dumpinfo (struct cpu *cpu) |
void | mips_cpu_list_available_types (void) |
int | mips_cpu_family_init (struct cpu_family *) |
struct mips_coproc * | mips_coproc_new (struct cpu *cpu, int coproc_nr) |
void | mips_coproc_tlb_set_entry (struct cpu *cpu, int entrynr, int size, uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1) |
void | coproc_register_read (struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select) |
void | coproc_register_write (struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select) |
void | coproc_tlbpr (struct cpu *cpu, int readflag) |
void | coproc_tlbwri (struct cpu *cpu, int randomflag) |
void | coproc_rfe (struct cpu *cpu) |
void | coproc_eret (struct cpu *cpu) |
void | coproc_function (struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running) |
int | memory_cache_R3000 (struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data) |
int | mips_memory_rw (struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags) |
int | translate_v2p_mmu3k (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
int | translate_v2p_mmu8k (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
int | translate_v2p_mmu10k (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
int | translate_v2p_mmu4100 (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
int | translate_v2p_generic (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
void | mips_unaligned_loadstore (struct cpu *cpu, struct mips_instr_call *ic, int is_left, int wlen, int store) |
int | mips_run_instr (struct cpu *cpu) |
void | mips_update_translation_table (struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page) |
void | mips_invalidate_translation_caches (struct cpu *cpu, uint64_t, int) |
void | mips_invalidate_code_translation (struct cpu *cpu, uint64_t, int) |
int | mips32_run_instr (struct cpu *cpu) |
void | mips32_update_translation_table (struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page) |
void | mips32_invalidate_translation_caches (struct cpu *cpu, uint64_t, int) |
void | mips32_invalidate_code_translation (struct cpu *cpu, uint64_t, int) |
#define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ |
Definition at line 176 of file cpu_mips.h.
#define DEFAULT_PCACHE_SIZE 15 /* 32 KB */ |
Definition at line 175 of file cpu_mips.h.
#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
Definition at line 173 of file cpu_mips.h.
#define INITIAL_PC 0xffffffffbfc00000ULL |
Definition at line 68 of file cpu_mips.h.
#define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) |
Definition at line 69 of file cpu_mips.h.
#define MIPS_ADDR_TO_PAGENR | ( | a | ) |
Definition at line 193 of file cpu_mips.h.
#define MIPS_FCSR_FCC0_SHIFT 23 |
Definition at line 95 of file cpu_mips.h.
#define MIPS_FCSR_FCC1_SHIFT 25 |
Definition at line 96 of file cpu_mips.h.
#define MIPS_FPU_FCCR 25 |
Definition at line 93 of file cpu_mips.h.
#define MIPS_FPU_FCIR 0 |
Definition at line 92 of file cpu_mips.h.
#define MIPS_FPU_FCSR 31 |
Definition at line 94 of file cpu_mips.h.
#define MIPS_GPR_A0 4 /* a0 */ |
Definition at line 138 of file cpu_mips.h.
#define MIPS_GPR_A1 5 /* a1 */ |
Definition at line 139 of file cpu_mips.h.
#define MIPS_GPR_A2 6 /* a2 */ |
Definition at line 140 of file cpu_mips.h.
#define MIPS_GPR_A3 7 /* a3 */ |
Definition at line 141 of file cpu_mips.h.
#define MIPS_GPR_AT 1 /* at */ |
Definition at line 135 of file cpu_mips.h.
#define MIPS_GPR_FP 30 /* fp */ |
Definition at line 164 of file cpu_mips.h.
#define MIPS_GPR_GP 28 /* gp */ |
Definition at line 162 of file cpu_mips.h.
#define MIPS_GPR_K0 26 /* k0 */ |
Definition at line 160 of file cpu_mips.h.
#define MIPS_GPR_K1 27 /* k1 */ |
Definition at line 161 of file cpu_mips.h.
#define MIPS_GPR_RA 31 /* ra */ |
Definition at line 165 of file cpu_mips.h.
#define MIPS_GPR_S0 16 /* s0 */ |
Definition at line 150 of file cpu_mips.h.
#define MIPS_GPR_S1 17 /* s1 */ |
Definition at line 151 of file cpu_mips.h.
#define MIPS_GPR_S2 18 /* s2 */ |
Definition at line 152 of file cpu_mips.h.
#define MIPS_GPR_S3 19 /* s3 */ |
Definition at line 153 of file cpu_mips.h.
#define MIPS_GPR_S4 20 /* s4 */ |
Definition at line 154 of file cpu_mips.h.
#define MIPS_GPR_S5 21 /* s5 */ |
Definition at line 155 of file cpu_mips.h.
#define MIPS_GPR_S6 22 /* s6 */ |
Definition at line 156 of file cpu_mips.h.
#define MIPS_GPR_S7 23 /* s7 */ |
Definition at line 157 of file cpu_mips.h.
#define MIPS_GPR_SP 29 /* sp */ |
Definition at line 163 of file cpu_mips.h.
#define MIPS_GPR_T0 8 /* t0 */ |
Definition at line 142 of file cpu_mips.h.
#define MIPS_GPR_T1 9 /* t1 */ |
Definition at line 143 of file cpu_mips.h.
#define MIPS_GPR_T2 10 /* t2 */ |
Definition at line 144 of file cpu_mips.h.
#define MIPS_GPR_T3 11 /* t3 */ |
Definition at line 145 of file cpu_mips.h.
#define MIPS_GPR_T4 12 /* t4 */ |
Definition at line 146 of file cpu_mips.h.
#define MIPS_GPR_T5 13 /* t5 */ |
Definition at line 147 of file cpu_mips.h.
#define MIPS_GPR_T6 14 /* t6 */ |
Definition at line 148 of file cpu_mips.h.
#define MIPS_GPR_T7 15 /* t7 */ |
Definition at line 149 of file cpu_mips.h.
#define MIPS_GPR_T8 24 /* t8 */ |
Definition at line 158 of file cpu_mips.h.
#define MIPS_GPR_T9 25 /* t9 */ |
Definition at line 159 of file cpu_mips.h.
#define MIPS_GPR_V0 2 /* v0 */ |
Definition at line 136 of file cpu_mips.h.
#define MIPS_GPR_V1 3 /* v1 */ |
Definition at line 137 of file cpu_mips.h.
#define MIPS_GPR_ZERO 0 /* zero */ |
Definition at line 134 of file cpu_mips.h.
#define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
Definition at line 190 of file cpu_mips.h.
#define MIPS_IC_ENTRIES_SHIFT 10 |
Definition at line 186 of file cpu_mips.h.
#define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
Definition at line 189 of file cpu_mips.h.
#define MIPS_L2N 17 |
Definition at line 196 of file cpu_mips.h.
#define MIPS_L3N 18 |
Definition at line 197 of file cpu_mips.h.
#define MIPS_MAX_VPH_TLB_ENTRIES 192 |
Definition at line 199 of file cpu_mips.h.
#define MIPS_N_IC_ARGS 3 |
Definition at line 188 of file cpu_mips.h.
#define MIPS_PC_TO_IC_ENTRY | ( | a | ) |
Definition at line 191 of file cpu_mips.h.
#define MIPS_REGISTER_NAMES |
Definition at line 128 of file cpu_mips.h.
#define N_HI6 64 |
Definition at line 167 of file cpu_mips.h.
#define N_MIPS_COPROC_REGS 32 |
Definition at line 78 of file cpu_mips.h.
#define N_MIPS_COPROCS 4 |
Definition at line 113 of file cpu_mips.h.
#define N_MIPS_FCRS 32 |
Definition at line 91 of file cpu_mips.h.
#define N_MIPS_FPRS 32 /* Floating point registers */ |
Definition at line 116 of file cpu_mips.h.
#define N_MIPS_GPRS 32 /* General purpose registers */ |
Definition at line 115 of file cpu_mips.h.
#define N_REGIMM 32 |
Definition at line 169 of file cpu_mips.h.
#define N_SPECIAL 64 |
Definition at line 168 of file cpu_mips.h.
#define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) |
Definition at line 98 of file cpu_mips.h.
#define R3000_TAG_DIRTY 2 |
Definition at line 183 of file cpu_mips.h.
#define R3000_TAG_VALID 1 |
Definition at line 182 of file cpu_mips.h.
void coproc_eret | ( | struct cpu * | cpu | ) |
Definition at line 1952 of file cpu_mips_coproc.cc.
References cpu::cd, COP0_EPC, COP0_ERROREPC, COP0_STATUS, mips_cpu::coproc, cpu::delay_slot, cpu::mips, cpu::pc, mips_coproc::reg, mips_cpu::rmw, STATUS_ERL, and STATUS_EXL.
void coproc_function | ( | struct cpu * | cpu, |
struct mips_coproc * | cp, | ||
int | cpnr, | ||
uint32_t | function, | ||
int | unassemble_only, | ||
int | running | ||
) |
Definition at line 1976 of file cpu_mips_coproc.cc.
References cpu::cd, COPz_DMFCz, COPz_MFCz, mips_cpu::cpu_type, debug, EXCEPTION_CPU, fatal(), mips_cpu_type_def::flags, cpu::mips, mips_cpu_exception(), NOFPU, op, and cpu::pc.
Referenced by X().
void coproc_register_read | ( | struct cpu * | cpu, |
struct mips_coproc * | cp, | ||
int | reg_nr, | ||
uint64_t * | ptr, | ||
int | select | ||
) |
Definition at line 583 of file cpu_mips_coproc.cc.
References cpu::cd, COP0_BADVADDR, COP0_CACHEERR, COP0_CAUSE, COP0_COMPARE, COP0_CONFIG, mips_cpu::cop0_config_select1, COP0_CONTEXT, COP0_COUNT, COP0_DEBUG, COP0_DESAVE, COP0_ENTRYHI, COP0_ENTRYLO0, COP0_ENTRYLO1, COP0_EPC, COP0_ERRCTL, COP0_ERROREPC, COP0_INDEX, COP0_LLADDR, COP0_PAGEMASK, COP0_PERFCNT, COP0_PRID, COP0_RANDOM, COP0_RESERV22, COP0_STATUS, COP0_TAGDATA_HI, COP0_TAGDATA_LO, COP0_WATCHHI, COP0_WATCHLO, COP0_WIRED, COP0_XCONTEXT, mips_coproc::coproc_nr, mips_cpu::count_register_read_count, cpu::cpu_id, fatal(), cpu::mips, and mips_coproc::reg.
Referenced by X().
void coproc_register_write | ( | struct cpu * | cpu, |
struct mips_coproc * | cp, | ||
int | reg_nr, | ||
uint64_t * | ptr, | ||
int | flag64, | ||
int | select | ||
) |
Definition at line 659 of file cpu_mips_coproc.cc.
References cpu::cd, CONTEXT_BADVPN2_MASK, CONTEXT_BADVPN2_MASK_R4100, COP0_BADVADDR, COP0_COMPARE, COP0_CONTEXT, COP0_COUNT, COP0_ENTRYLO0, COP0_ENTRYLO1, COP0_INDEX, COP0_PAGEMASK, COP0_RANDOM, COP0_WIRED, mips_coproc::coproc_nr, cpu::cpu_id, mips_cpu::cpu_type, machine::emulated_hz, ENTRYLO_C_MASK, ENTRYLO_D, ENTRYLO_G, ENTRYLO_PFN_MASK, ENTRYLO_V, fatal(), INDEX_MASK, cpu::machine, cpu::mips, MIPS_R4100, MMU3K, MMU4K, mips_cpu_type_def::mmu_model, mips_coproc::nr_of_tlbs, PAGEMASK_SHIFT, R2K3K_CONTEXT_BADVPN_MASK, R2K3K_ENTRYLO_D, R2K3K_ENTRYLO_G, R2K3K_ENTRYLO_N, R2K3K_ENTRYLO_PFN_MASK, R2K3K_ENTRYLO_V, mips_coproc::reg, mips_cpu_type_def::rev, mips_cpu::timer, and timer_add().
Referenced by X().
void coproc_rfe | ( | struct cpu * | cpu | ) |
void coproc_tlbpr | ( | struct cpu * | cpu, |
int | readflag | ||
) |
Definition at line 1489 of file cpu_mips_coproc.cc.
References cpu::cd, COP0_ENTRYHI, COP0_ENTRYLO0, COP0_ENTRYLO1, COP0_INDEX, COP0_PAGEMASK, mips_cpu::coproc, mips_cpu::cpu_type, ENTRYHI_ASID, ENTRYHI_R_MASK, ENTRYHI_VPN2_MASK, ENTRYHI_VPN2_MASK_R10K, ENTRYLO_G, fatal(), mips_tlb::hi, if(), INDEX_MASK, INDEX_P, mips_tlb::lo0, mips_tlb::lo1, mips_tlb::mask, cpu::mips, MIPS_R4100, MMU10K, MMU3K, mips_cpu_type_def::mmu_model, mips_coproc::nr_of_tlbs, R2K3K_ENTRYHI_ASID_MASK, R2K3K_ENTRYHI_VPN_MASK, R2K3K_ENTRYLO_G, R2K3K_INDEX_MASK, R2K3K_INDEX_SHIFT, mips_coproc::reg, mips_cpu_type_def::rev, TLB_G, and mips_coproc::tlbs.
Referenced by X().
void coproc_tlbwri | ( | struct cpu * | cpu, |
int | randomflag | ||
) |
Definition at line 1608 of file cpu_mips_coproc.cc.
References cpu::cd, COP0_ENTRYHI, COP0_ENTRYLO0, COP0_ENTRYLO1, COP0_INDEX, COP0_PAGEMASK, COP0_RANDOM, COP0_STATUS, COP0_WIRED, mips_cpu::coproc, mips_cpu::cpu_type, ENTRYHI_ASID, ENTRYHI_R_MASK, ENTRYHI_VPN2_MASK, ENTRYHI_VPN2_MASK_R10K, ENTRYLO_D, ENTRYLO_G, ENTRYLO_PFN_MASK, ENTRYLO_PFN_SHIFT, ENTRYLO_V, EXC3K, mips_cpu_type_def::exc_model, fatal(), mips_tlb::hi, INDEX_MASK, cpu::invalidate_code_translation, INVALIDATE_PADDR, cpu::invalidate_translation_caches, INVALIDATE_VADDR, cpu::is_32bit, mips_cpu::last_written_tlb_index, mips_tlb::lo0, mips_tlb::lo1, mips_tlb::mask, cpu::mem, memory_paddr_to_hostaddr(), cpu::mips, MIPS1_ISOL_CACHES, MIPS_R4100, MMU10K, MMU3K, mips_cpu_type_def::mmu_model, mips_coproc::nr_of_tlbs, R2K3K_ENTRYHI_ASID_MASK, R2K3K_ENTRYHI_VPN_MASK, R2K3K_ENTRYLO_D, R2K3K_ENTRYLO_G, R2K3K_ENTRYLO_PFN_MASK, R2K3K_ENTRYLO_V, R2K3K_INDEX_MASK, R2K3K_INDEX_SHIFT, R2K3K_RANDOM_MASK, R2K3K_RANDOM_SHIFT, RANDOM_MASK, mips_coproc::reg, mips_cpu_type_def::rev, TLB_G, mips_coproc::tlbs, and cpu::update_translation_table.
Referenced by X().
int memory_cache_R3000 | ( | struct cpu * | cpu, |
int | cache, | ||
uint64_t | paddr, | ||
int | writeflag, | ||
size_t | len, | ||
unsigned char * | data | ||
) |
Definition at line 43 of file memory_mips.cc.
References addr, mips_cpu::cache, CACHE_DATA, mips_cpu::cache_last_paddr, mips_cpu::cache_mask, CACHE_NONE, cpu::cd, COP0_STATUS, mips_cpu::coproc, data, MEM_READ, cpu::mips, MIPS1_CACHE_MISS, MIPS1_ISOL_CACHES, and mips_coproc::reg.
Referenced by MEMORY_RW().
void mips32_invalidate_code_translation | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
void mips32_invalidate_translation_caches | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
int mips32_run_instr | ( | struct cpu * | cpu | ) |
void mips32_update_translation_table | ( | struct cpu * | cpu, |
uint64_t | vaddr_page, | ||
unsigned char * | host_page, | ||
int | writeflag, | ||
uint64_t | paddr_page | ||
) |
struct mips_coproc* mips_coproc_new | ( | struct cpu * | cpu, |
int | coproc_nr | ||
) |
Definition at line 356 of file cpu_mips_coproc.cc.
References cpu::cd, CHECK_ALLOCATION, COP0_PAGEMASK, COP0_PRID, COP0_STATUS, COP0_WIRED, mips_coproc::coproc_nr, mips_cpu::cpu_type, cpu::machine, cpu::mips, MIPS_R5900, mips_cpu_type_def::nr_of_tlb_entries, mips_coproc::nr_of_tlbs, machine::prom_emulation, R5900_STATUS_EIE, mips_coproc::reg, mips_cpu_type_def::rev, STATUS_BEV, STATUS_CU_SHIFT, mips_cpu_type_def::sub, mips_coproc::tlbs, and zeroed_alloc().
Referenced by MACHINE_SETUP().
void mips_coproc_tlb_set_entry | ( | struct cpu * | cpu, |
int | entrynr, | ||
int | size, | ||
uint64_t | vaddr, | ||
uint64_t | paddr0, | ||
uint64_t | paddr1, | ||
int | valid0, | ||
int | valid1, | ||
int | dirty0, | ||
int | dirty1, | ||
int | global, | ||
int | asid, | ||
int | cachealgo0, | ||
int | cachealgo1 | ||
) |
Definition at line 438 of file cpu_mips_coproc.cc.
References cpu::cd, mips_cpu::coproc, mips_cpu::cpu_type, ENTRYHI_ASID, ENTRYHI_R_MASK, ENTRYHI_VPN2_MASK, ENTRYHI_VPN2_MASK_R10K, ENTRYLO_C_MASK, ENTRYLO_C_SHIFT, ENTRYLO_D, ENTRYLO_G, ENTRYLO_PFN_MASK, ENTRYLO_PFN_SHIFT, ENTRYLO_V, mips_tlb::hi, mips_tlb::lo0, mips_tlb::lo1, mips_tlb::mask, cpu::mips, MMU10K, MMU3K, mips_cpu_type_def::mmu_model, mips_coproc::nr_of_tlbs, R2K3K_ENTRYHI_ASID_MASK, R2K3K_ENTRYHI_ASID_SHIFT, R2K3K_ENTRYHI_VPN_MASK, R2K3K_ENTRYLO_D, R2K3K_ENTRYLO_G, R2K3K_ENTRYLO_N, R2K3K_ENTRYLO_PFN_MASK, R2K3K_ENTRYLO_V, TLB_G, and mips_coproc::tlbs.
int mips_cpu_disassemble_instr | ( | struct cpu * | cpu, |
unsigned char * | instr, | ||
int | running, | ||
uint64_t | addr | ||
) |
Definition at line 701 of file cpu_mips.cc.
References addr, cpu::byte_order, cpu::cpu_id, debug, cpu::delay_slot, EMUL_BIG_ENDIAN, get_symbol_name(), HI6_SPECIAL, instr, cpu::is_32bit, cpu::machine, machine::ncpus, cpu::pc, SPECIAL_DSLL, SPECIAL_DSLL32, SPECIAL_DSRA, SPECIAL_DSRA32, SPECIAL_DSRL, SPECIAL_DSRL32, SPECIAL_SLL, SPECIAL_SRA, SPECIAL_SRL, and machine::symbol_context.
void mips_cpu_dumpinfo | ( | struct cpu * | cpu | ) |
Definition at line 349 of file cpu_mips.cc.
References cpu::byte_order, cpu::cd, mips_cpu::cpu_type, debug, DEBUG_INDENTATION, debug_indentation(), EMUL_BIG_ENDIAN, cpu::is_32bit, mips_cpu_type_def::isa_level, mips_cpu_type_def::isa_revision, cpu::mips, mips_cpu_type_def::nr_of_tlb_entries, mips_cpu_type_def::pdcache, mips_cpu_type_def::pdlinesize, mips_cpu_type_def::pdways, mips_cpu_type_def::picache, mips_cpu_type_def::pilinesize, mips_cpu_type_def::piways, mips_cpu_type_def::scache, mips_cpu_type_def::slinesize, and mips_cpu_type_def::sways.
void mips_cpu_exception | ( | struct cpu * | cpu, |
int | exccode, | ||
int | tlb, | ||
uint64_t | vaddr, | ||
int | coproc_nr, | ||
uint64_t | vaddr_vpn2, | ||
int | vaddr_asid, | ||
int | x_64 | ||
) |
Definition at line 1719 of file cpu_mips.cc.
References cpu::cd, mips_cpu::coproc, cpu::cpu_id, mips_cpu::cpu_type, debug, mips_cpu_type_def::exc_model, get_symbol_name(), cpu::is_halted, cpu::machine, cpu::mips, machine::ncpus, cpu::pc, quiet_mode, reg, mips_coproc::reg, and machine::symbol_context.
Referenced by cop0_availability_check(), coproc_function(), MEMORY_RW(), TRANSLATE_ADDRESS(), and X().
int mips_cpu_family_init | ( | struct cpu_family * | ) |
int mips_cpu_instruction_has_delayslot | ( | struct cpu * | cpu, |
unsigned char * | ib | ||
) |
Definition at line 445 of file cpu_mips.cc.
References BE32_TO_HOST, cpu::byte_order, EMUL_LITTLE_ENDIAN, HI6_BEQ, HI6_BEQL, HI6_BGTZ, HI6_BGTZL, HI6_BLEZ, HI6_BLEZL, HI6_BNE, HI6_BNEL, HI6_J, HI6_JAL, HI6_REGIMM, HI6_SPECIAL, LE32_TO_HOST, REGIMM_BGEZ, REGIMM_BGEZAL, REGIMM_BGEZALL, REGIMM_BGEZL, REGIMM_BLTZ, REGIMM_BLTZAL, REGIMM_BLTZALL, REGIMM_BLTZL, SPECIAL_JALR, and SPECIAL_JR.
void mips_cpu_interrupt_assert | ( | struct interrupt * | interrupt | ) |
Definition at line 1692 of file cpu_mips.cc.
References cpu::cd, COP0_CAUSE, mips_cpu::coproc, interrupt::extra, interrupt::line, cpu::mips, and mips_coproc::reg.
void mips_cpu_interrupt_deassert | ( | struct interrupt * | interrupt | ) |
Definition at line 1697 of file cpu_mips.cc.
References cpu::cd, COP0_CAUSE, mips_cpu::coproc, interrupt::extra, interrupt::line, cpu::mips, and mips_coproc::reg.
void mips_cpu_list_available_types | ( | void | ) |
Definition at line 423 of file cpu_mips.cc.
void mips_cpu_register_dump | ( | struct cpu * | cpu, |
int | gprs, | ||
int | coprocs | ||
) |
Definition at line 1502 of file cpu_mips.cc.
References cpu::cd, cpu::cpu_id, mips_cpu::cpu_type, debug, get_symbol_name(), mips_cpu::hi, mips_cpu::hi1, cpu::is_32bit, mips_cpu::lo, mips_cpu::lo1, cpu::machine, cpu::mips, MIPS_GPR_ZERO, MIPS_R5900, cpu::pc, mips_cpu_type_def::rev, and machine::symbol_context.
void mips_cpu_register_match | ( | struct machine * | m, |
char * | name, | ||
int | writeflag, | ||
uint64_t * | valuep, | ||
int * | match_register | ||
) |
void mips_cpu_tlbdump | ( | struct machine * | m, |
int | x, | ||
int | rawflag | ||
) |
Definition at line 501 of file cpu_mips.cc.
References cpu::cd, COP0_INDEX, COP0_RANDOM, COP0_WIRED, mips_cpu::coproc, mips_cpu::cpu_type, machine::cpus, ENTRYHI_ASID, ENTRYLO_D, ENTRYLO_PFN_MASK, ENTRYLO_PFN_SHIFT, ENTRYLO_V, mips_tlb::hi, INDEX_MASK, cpu::is_32bit, mips_cpu_type_def::isa_level, mips_tlb::lo0, mips_tlb::lo1, mips_tlb::mask, cpu::mips, MIPS_R4100, MMU32, MMU3K, mips_cpu_type_def::mmu_model, machine::ncpus, R2K3K_ENTRYHI_ASID_MASK, R2K3K_ENTRYHI_ASID_SHIFT, R2K3K_ENTRYHI_VPN_MASK, R2K3K_ENTRYLO_D, R2K3K_ENTRYLO_G, R2K3K_ENTRYLO_N, R2K3K_ENTRYLO_PFN_MASK, R2K3K_ENTRYLO_V, R2K3K_INDEX_MASK, R2K3K_INDEX_SHIFT, R2K3K_RANDOM_MASK, R2K3K_RANDOM_SHIFT, RANDOM_MASK, mips_coproc::reg, mips_cpu_type_def::rev, TLB_G, and mips_coproc::tlbs.
void mips_invalidate_code_translation | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
void mips_invalidate_translation_caches | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
int mips_memory_rw | ( | struct cpu * | cpu, |
struct memory * | mem, | ||
uint64_t | vaddr, | ||
unsigned char * | data, | ||
size_t | len, | ||
int | writeflag, | ||
int | cache_flags | ||
) |
int mips_run_instr | ( | struct cpu * | cpu | ) |
void mips_unaligned_loadstore | ( | struct cpu * | cpu, |
struct mips_instr_call * | ic, | ||
int | is_left, | ||
int | wlen, | ||
int | store | ||
) |
Definition at line 44 of file cpu_mips_instr_unaligned.cc.
References addr, cpu::byte_order, CACHE_DATA, CAUSE_EXCCODE_MASK, CAUSE_EXCCODE_SHIFT, cpu::cd, COP0_CAUSE, mips_cpu::coproc, EMUL_LITTLE_ENDIAN, EXCEPTION_TLBS, ic, cpu::is_32bit, cpu::mem, MEM_READ, MEM_WRITE, cpu::memory_rw, cpu::mips, MIPS_IC_ENTRIES_PER_PAGE, MIPS_INSTR_ALIGNMENT_SHIFT, cpu::pc, and mips_coproc::reg.
Referenced by X().
void mips_update_translation_table | ( | struct cpu * | cpu, |
uint64_t | vaddr_page, | ||
unsigned char * | host_page, | ||
int | writeflag, | ||
uint64_t | paddr_page | ||
) |
int translate_v2p_generic | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |
int translate_v2p_mmu10k | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |
int translate_v2p_mmu3k | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |
int translate_v2p_mmu4100 | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |
int translate_v2p_mmu8k | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |