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cpu_mips.h
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1 #ifndef CPU_MIPS_H
2 #define CPU_MIPS_H
3 
4 /*
5  * Copyright (C) 2003-2010 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * MIPS CPU definitions.
32  */
33 
34 #include "interrupt.h"
35 #include "misc.h"
36 
37 struct cpu_family;
38 struct emul;
39 struct machine;
40 struct timer;
41 
42 /*
43  * CPU type definitions: See mips_cpu_types.h.
44  */
45 
46 struct mips_cpu_type_def {
47  const char *name;
48  int rev;
49  int sub;
50  char flags;
51  char exc_model; /* EXC3K or EXC4K */
52  char mmu_model; /* MMU3K or MMU4K */
53  char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
54  char isa_revision; /* 1 or 2 (for MIPS32/64) */
55  int nr_of_tlb_entries; /* 32, 48, 64, ... */
56  char instrs_per_cycle; /* simplified, 1, 2, or 4 */
57  int picache;
58  int pilinesize;
59  int piways;
60  int pdcache;
61  int pdlinesize;
62  int pdways;
63  int scache;
64  int slinesize;
65  int sways;
66 };
67 
68 #define INITIAL_PC 0xffffffffbfc00000ULL
69 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
70 
71 
72 /*
73  * Coproc 0:
74  *
75  * NOTE:
76  * On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
77  */
78 #define N_MIPS_COPROC_REGS 32
79 struct mips_tlb {
80  uint64_t hi;
81  uint64_t lo0;
82  uint64_t lo1;
83  uint64_t mask;
84 };
85 
86 
87 /*
88  * Coproc 1:
89  */
90 /* FPU control registers: */
91 #define N_MIPS_FCRS 32
92 #define MIPS_FPU_FCIR 0
93 #define MIPS_FPU_FCCR 25
94 #define MIPS_FPU_FCSR 31
95 #define MIPS_FCSR_FCC0_SHIFT 23
96 #define MIPS_FCSR_FCC1_SHIFT 25
97 
98 #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20)
99 
100 struct mips_coproc {
103 
104  /* Only for COP0: */
105  struct mips_tlb *tlbs;
107 
108  /* Only for COP1: floating point control registers */
109  /* (Maybe also for COP0?) */
110  uint64_t fcr[N_MIPS_FCRS];
111 };
112 
113 #define N_MIPS_COPROCS 4
114 
115 #define N_MIPS_GPRS 32 /* General purpose registers */
116 #define N_MIPS_FPRS 32 /* Floating point registers */
117 
118 /*
119  * These should all be 2 characters wide:
120  *
121  * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
122  * are used to pass arguments and are then called "a4".."a7".
123  *
124  * TODO: Should there be two different variants of this? It's not really
125  * possible to figure out in some easy way if the code running was
126  * written for a 32-bit or 64-bit ABI.
127  */
128 #define MIPS_REGISTER_NAMES { \
129  "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
130  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
131  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
132  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
133 
134 #define MIPS_GPR_ZERO 0 /* zero */
135 #define MIPS_GPR_AT 1 /* at */
136 #define MIPS_GPR_V0 2 /* v0 */
137 #define MIPS_GPR_V1 3 /* v1 */
138 #define MIPS_GPR_A0 4 /* a0 */
139 #define MIPS_GPR_A1 5 /* a1 */
140 #define MIPS_GPR_A2 6 /* a2 */
141 #define MIPS_GPR_A3 7 /* a3 */
142 #define MIPS_GPR_T0 8 /* t0 */
143 #define MIPS_GPR_T1 9 /* t1 */
144 #define MIPS_GPR_T2 10 /* t2 */
145 #define MIPS_GPR_T3 11 /* t3 */
146 #define MIPS_GPR_T4 12 /* t4 */
147 #define MIPS_GPR_T5 13 /* t5 */
148 #define MIPS_GPR_T6 14 /* t6 */
149 #define MIPS_GPR_T7 15 /* t7 */
150 #define MIPS_GPR_S0 16 /* s0 */
151 #define MIPS_GPR_S1 17 /* s1 */
152 #define MIPS_GPR_S2 18 /* s2 */
153 #define MIPS_GPR_S3 19 /* s3 */
154 #define MIPS_GPR_S4 20 /* s4 */
155 #define MIPS_GPR_S5 21 /* s5 */
156 #define MIPS_GPR_S6 22 /* s6 */
157 #define MIPS_GPR_S7 23 /* s7 */
158 #define MIPS_GPR_T8 24 /* t8 */
159 #define MIPS_GPR_T9 25 /* t9 */
160 #define MIPS_GPR_K0 26 /* k0 */
161 #define MIPS_GPR_K1 27 /* k1 */
162 #define MIPS_GPR_GP 28 /* gp */
163 #define MIPS_GPR_SP 29 /* sp */
164 #define MIPS_GPR_FP 30 /* fp */
165 #define MIPS_GPR_RA 31 /* ra */
166 
167 #define N_HI6 64
168 #define N_SPECIAL 64
169 #define N_REGIMM 32
170 
171 
172 /* An "impossible" paddr: */
173 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL
174 
175 #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */
176 #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */
177 
179  uint32_t tag_paddr;
181 };
182 #define R3000_TAG_VALID 1
183 #define R3000_TAG_DIRTY 2
184 
185 
186 #define MIPS_IC_ENTRIES_SHIFT 10
187 
188 #define MIPS_N_IC_ARGS 3
189 #define MIPS_INSTR_ALIGNMENT_SHIFT 2
190 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
191 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
192  & (MIPS_IC_ENTRIES_PER_PAGE-1))
193 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
194  + MIPS_INSTR_ALIGNMENT_SHIFT))
195 
196 #define MIPS_L2N 17
197 #define MIPS_L3N 18
198 
199 #define MIPS_MAX_VPH_TLB_ENTRIES 192
200 
201 DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
202 DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
203 
204 
205 struct mips_cpu {
206  struct mips_cpu_type_def cpu_type;
207 
208  /* General purpose registers: */
209  uint64_t gpr[N_MIPS_GPRS];
210 
211  /* Dummy destination register when writing to the zero register: */
212  uint64_t scratch;
213 
214  /* Special purpose registers: */
215  uint64_t hi;
216  uint64_t lo;
217 
218  /* Coprocessors: */
219  struct mips_coproc *coproc[N_MIPS_COPROCS];
221 
223 
224  /* Count/compare timer: */
228  struct interrupt irq_compare;
229  struct timer *timer;
230 
231  int rmw; /* Read-Modify-Write */
232  uint64_t rmw_len; /* Length of rmw modification */
233  uint64_t rmw_addr; /* Address of rmw modification */
234 
235  /*
236  * NOTE: The R5900 has 128-bit registers. I'm not really sure
237  * whether they are used a lot or not, at least with code produced
238  * with gcc they are not. An important case however is lq and sq
239  * (load and store of 128-bit values). These "upper halves" of R5900
240  * quadwords can be used in those cases.
241  *
242  * hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
243  * sa is a 32-bit "shift amount" register.
244  *
245  * TODO: Generalize this.
246  */
247  uint64_t gpr_quadhi[N_MIPS_GPRS];
248  uint64_t hi1;
249  uint64_t lo1;
250  uint32_t r5900_sa;
251 
252 
253  /*
254  * Data and Instruction caches:
255  */
256 
257  /* Cache sizes: (1 << x) x=0 for default values */
258  /* This is legacy stuff. TODO: Clean up! */
265 
266  unsigned char *cache[2];
267  void *cache_tags[2];
268  uint64_t cache_last_paddr[2];
269  int cache_size[2];
270  int cache_linesize[2];
271  int cache_mask[2];
272 
273 
274  /*
275  * Instruction translation cache and Virtual->Physical->Host
276  * address translation:
277  */
278  DYNTRANS_ITC(mips)
279  VPH_TLBS(mips,MIPS)
280  VPH32(mips,MIPS)
281  VPH64(mips,MIPS)
282 };
283 
284 
285 /* cpu_mips.c: */
288 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
289 void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
290 void mips_cpu_register_match(struct machine *m, char *name,
291  int writeflag, uint64_t *valuep, int *match_register);
292 void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
293 int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
294  int running, uint64_t addr);
295 void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
296  /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2,
297  int vaddr_asid, int x_64);
298 int mips_cpu_run(struct emul *emul, struct machine *machine);
299 void mips_cpu_dumpinfo(struct cpu *cpu);
301 int mips_cpu_family_init(struct cpu_family *);
302 
303 
304 /* cpu_mips_coproc.c: */
305 struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr);
306 void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
307  uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
308  int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
309  int cachealgo0, int cachealgo1);
310 void coproc_register_read(struct cpu *cpu,
311  struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
312 void coproc_register_write(struct cpu *cpu,
313  struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
314  int select);
315 void coproc_tlbpr(struct cpu *cpu, int readflag);
316 void coproc_tlbwri(struct cpu *cpu, int randomflag);
317 void coproc_rfe(struct cpu *cpu);
318 void coproc_eret(struct cpu *cpu);
319 void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
320  uint32_t function, int unassemble_only, int running);
321 
322 
323 /* memory_mips.c: */
324 int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
325  int writeflag, size_t len, unsigned char *data);
326 int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
327  unsigned char *data, size_t len, int writeflag, int cache_flags);
328 
329 int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
330  uint64_t *return_addr, int flags);
331 int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
332  uint64_t *return_addr, int flags);
333 int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
334  uint64_t *return_addr, int flags);
335 int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
336  uint64_t *return_addr, int flags);
337 int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
338  uint64_t *return_addr, int flags);
339 
340 
341 /* Dyntrans unaligned load/store: */
342 void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
343  int is_left, int wlen, int store);
344 
345 
346 int mips_run_instr(struct cpu *cpu);
347 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
348  unsigned char *host_page, int writeflag, uint64_t paddr_page);
349 void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
350 void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
351 int mips32_run_instr(struct cpu *cpu);
352 void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
353  unsigned char *host_page, int writeflag, uint64_t paddr_page);
354 void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
355 void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
356 
357 
358 #endif /* CPU_MIPS_H */
mips_cpu::last_written_tlb_index
int last_written_tlb_index
Definition: cpu_mips.h:222
mips_cpu::rmw_addr
uint64_t rmw_addr
Definition: cpu_mips.h:233
mips_cpu_type_def::pdcache
int pdcache
Definition: MIPS_CPUComponent.h:132
mips_cpu::timer
struct timer * timer
Definition: cpu_mips.h:229
mips_coproc::reg
uint64_t reg[N_MIPS_COPROC_REGS]
Definition: cpu_mips.h:102
mips_cpu::cache_pdcache
int cache_pdcache
Definition: cpu_mips.h:260
data
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Definition: siireg.h:79
instr
#define instr(n)
Definition: tmp_alpha_head.cc:43
mips_cpu::compare_interrupts_pending
int compare_interrupts_pending
Definition: cpu_mips.h:226
mips_cpu::hi
uint64_t hi
Definition: cpu_mips.h:215
mips_cpu::rmw_len
uint64_t rmw_len
Definition: cpu_mips.h:232
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char isa_revision
Definition: cpu_mips.h:54
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void coproc_tlbpr(struct cpu *cpu, int readflag)
Definition: cpu_mips_coproc.cc:1489
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#define VPH32(arch, ARCH)
Definition: cpu.h:189
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int cache_secondary_linesize
Definition: cpu_mips.h:264
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Definition: timer.cc:45
mips_cpu_tlbdump
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
Definition: cpu_mips.cc:501
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Definition: memory.h:75
N_MIPS_FCRS
#define N_MIPS_FCRS
Definition: cpu_mips.h:91
mips_cpu_type_def::sways
int sways
Definition: MIPS_CPUComponent.h:137
mips_cpu::cache_secondary
int cache_secondary
Definition: cpu_mips.h:261
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void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
Definition: cpu_mips_coproc.cc:583
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void coproc_rfe(struct cpu *cpu)
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int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, int running, uint64_t addr)
Definition: cpu_mips.cc:701
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struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
Definition: cpu_mips_coproc.cc:356
mips_coproc::tlbs
struct mips_tlb * tlbs
Definition: cpu_mips.h:105
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Definition: cpu_mips.cc:423
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int mips32_run_instr(struct cpu *cpu)
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#define N_MIPS_COPROC_REGS
Definition: cpu_mips.h:78
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Definition: cpu_mips.h:79
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int pilinesize
Definition: MIPS_CPUComponent.h:130
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#define DYNTRANS_MISC64_DECLARATIONS(arch, ARCH, tlbindextype)
Definition: cpu.h:95
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void coproc_eret(struct cpu *cpu)
Definition: cpu_mips_coproc.cc:1952
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int cache_picache_linesize
Definition: cpu_mips.h:262
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Definition: cpu_mips.cc:1692
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void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
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int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
DYNTRANS_MISC_DECLARATIONS
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
Definition: cpu.h:72
addr
uint32_t addr
Definition: tmp_arm_multi.cc:52
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Definition: MIPS_CPUComponent.h:118
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void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, int is_left, int wlen, int store)
Definition: cpu_mips_instr_unaligned.cc:44
mips32_update_translation_table
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
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char isa_level
Definition: cpu_mips.h:53
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void mips_cpu_dumpinfo(struct cpu *cpu)
Definition: cpu_mips.cc:349
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Definition: cpu_mips.h:82
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Definition: cpu_mips.h:248
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int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
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void coproc_register_write(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select)
Definition: cpu_mips_coproc.cc:659
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Definition: MIPS_CPUComponent.h:135
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#define DYNTRANS_ITC(arch)
Definition: cpu.h:143
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int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
Definition: cpu_mips.cc:445
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uint64_t fcr[N_MIPS_FCRS]
Definition: cpu_mips.h:110
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int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data)
Definition: memory_mips.cc:43
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int32_t count_register_read_count
Definition: cpu_mips.h:227
interrupt.h
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void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
misc.h
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uint32_t tag_paddr
Definition: cpu_mips.h:179
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#define VPH_TLBS(arch, ARCH)
Definition: cpu.h:157
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Definition: machine.h:97
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Definition: tmp_arm_multi.cc:50
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Definition: cpu_mips.h:81
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int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
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Definition: MIPS_CPUComponent.h:129
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Definition: cpu_mips.h:249
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const char * name
Definition: MIPS_CPUComponent.h:119
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Definition: cpu_mips.h:225
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Definition: cpu_mips.h:180
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Definition: MIPS_CPUComponent.h:120
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Definition: cpu_mips.h:51
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int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
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void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
Definition: cpu_mips_coproc.cc:1976
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char mmu_model
Definition: cpu_mips.h:52
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Definition: cpu_mips_coproc.cc:438
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char instrs_per_cycle
Definition: cpu_mips.h:56
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Definition: cpu_mips.h:231
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void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
Definition: cpu_mips.cc:1719
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uint64_t cop0_config_select1
Definition: cpu_mips.h:220
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#define VPH64(arch, ARCH)
Definition: cpu.h:223
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int cache_pdcache_linesize
Definition: cpu_mips.h:263
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int cache_picache
Definition: cpu_mips.h:259
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void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
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int mips_cpu_run(struct emul *emul, struct machine *machine)
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Definition: cpu_mips.h:50
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int piways
Definition: MIPS_CPUComponent.h:131
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#define N_MIPS_COPROCS
Definition: cpu_mips.h:113
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uint64_t mask
Definition: cpu_mips.h:83
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Definition: emul.h:37
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void coproc_tlbwri(struct cpu *cpu, int randomflag)
Definition: cpu_mips_coproc.cc:1608
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Definition: interrupt.h:36
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