dec_kmin.h Source File

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dec_kmin.h
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1 /* gxemul: $Id: dec_kmin.h,v 1.3 2005-03-05 12:34:02 debug Exp $ */
2 
3 #ifndef MIPS_KMIN_H
4 #define MIPS_KMIN_H 1
5 
6 #include "tc_ioasicreg.h"
7 
8 /* $NetBSD: kmin.h,v 1.8 2000/02/29 04:41:55 nisimura Exp $ */
9 
10 /*-
11  * Copyright (c) 1992, 1993
12  * The Regents of the University of California. All rights reserved.
13  *
14  * This code is derived from software contributed to Berkeley by
15  * The Mach Operating System project at Carnegie-Mellon University,
16  * Ralph Campbell and Rick Macklem.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions
20  * are met:
21  * 1. Redistributions of source code must retain the above copyright
22  * notice, this list of conditions and the following disclaimer.
23  * 2. Redistributions in binary form must reproduce the above copyright
24  * notice, this list of conditions and the following disclaimer in the
25  * documentation and/or other materials provided with the distribution.
26  * 3. All advertising materials mentioning features or use of this software
27  * must display the following acknowledgement:
28  * This product includes software developed by the University of
29  * California, Berkeley and its contributors.
30  * 4. Neither the name of the University nor the names of its contributors
31  * may be used to endorse or promote products derived from this software
32  * without specific prior written permission.
33  *
34  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
35  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
38  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
44  * SUCH DAMAGE.
45  *
46  * @(#)kmin.h 8.1 (Berkeley) 6/10/93
47  */
48 
49 /*
50  * Mach Operating System
51  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
52  * All Rights Reserved.
53  *
54  * Permission to use, copy, modify and distribute this software and
55  * its documentation is hereby granted, provided that both the copyright
56  * notice and this permission notice appear in all copies of the
57  * software, derivative works or modified versions, and any portions
58  * thereof, and that both notices appear in supporting documentation.
59  *
60  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
61  * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
62  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
63  *
64  * Carnegie Mellon requests users of this software to return to
65  *
66  * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
67  * School of Computer Science
68  * Carnegie Mellon University
69  * Pittsburgh PA 15213-3890
70  *
71  * any improvements or extensions that they make and grant Carnegie the
72  * rights to redistribute these changes.
73  */
74 /*
75  * HISTORY
76  * Log: kmin.h,v
77  * Revision 2.3 92/03/02 18:33:43 rpd
78  * Split out the ASIC defns into separate file, which is
79  * in common with MAXine. Added some nitwits defines.
80  * [92/03/02 02:28:27 af]
81  *
82  * Revision 2.2 91/08/24 12:21:08 af
83  * Documented new SCSI registers, which were missing in the 3min prototype.
84  * [91/08/22 11:14:57 af]
85  *
86  * Created, from the DEC specs:
87  * "3MIN System Module Functional Specification" Revision 1.7
88  * Workstation Systems Engineering, Palo Alto, CA. Sept 14, 1990.
89  * "KN02BA Daughter Card Functional Specification" Revision 1.0
90  * Workstation Systems Engineering, Palo Alto, CA. Aug 14, 1990.
91  * [91/06/21 af]
92  *
93  */
94 /*
95  * File: kmin.h
96  * Author: Alessandro Forin, Carnegie Mellon University
97  * Date: 6/91
98  *
99  * Definitions specific to the KN02BA/KN02DA processors and 3MIN
100  * system module (54-20604-01)
101  */
102 
103 /*
104  * 3MIN's Physical address space
105  */
106 #define KMIN_PHYS_MIN 0x00000000 /* 512 Meg */
107 #define KMIN_PHYS_MAX 0x1fffffff
108 
109 /*
110  * Memory map
111  */
112 #define KMIN_PHYS_MEMORY_START 0x00000000
113 #define KMIN_PHYS_MEMORY_END 0x07ffffff /* 128 Meg in 8 slots */
114 
115 /*
116  * I/O map
117  */
118 #define KMIN_PHYS_RESERVED 0x08000000 /* Reserved */
119  /* 64 Meg */
120 
121 #define KMIN_PHYS_MREGS_START 0x0c000000 /* Memory control registers */
122 #define KMIN_PHYS_MREGS_END 0x0dffffff /* 32 Meg */
123 #define KMIN_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */
124 #define KMIN_PHYS_CREGS_END 0x0fffffff /* 32 Meg */
125 
126 #define KMIN_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */
127 #define KMIN_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */
128 
129 #define KMIN_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */
130 #define KMIN_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */
131 
132 #define KMIN_PHYS_TC_2_START 0x18000000 /* TURBOchannel, slot 2 */
133 #define KMIN_PHYS_TC_2_END 0x1bffffff /* 64 Meg, option2 */
134 
135 #define KMIN_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */
136 #define KMIN_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */
137 
138 #define KMIN_PHYS_TC_START KMIN_PHYS_TC_0_START
139 #define KMIN_PHYS_TC_END KMIN_PHYS_TC_3_END /* 256 Meg */
140 
141 #define KMIN_TC_NSLOTS 4
142 #define KMIN_TC_MIN 0
143 #define KMIN_TC_MAX 2 /* don't look at system slot */
144 
145 /*
146  * System module space (IOASIC)
147  */
148 #define KMIN_SYS_ASIC ( KMIN_PHYS_TC_3_START + 0x0000000 )
149 #define KMIN_SYS_ROM_START ( KMIN_SYS_ASIC + IOASIC_SLOT_0_START )
150 #define KMIN_SYS_ASIC_REGS ( KMIN_SYS_ASIC + IOASIC_SLOT_1_START )
151 #define KMIN_SYS_ETHER_ADDRESS ( KMIN_SYS_ASIC + IOASIC_SLOT_2_START )
152 #define KMIN_SYS_LANCE ( KMIN_SYS_ASIC + IOASIC_SLOT_3_START )
153 #define KMIN_SYS_SCC_0 ( KMIN_SYS_ASIC + IOASIC_SLOT_4_START )
154 #define KMIN_SYS_SCC_1 ( KMIN_SYS_ASIC + IOASIC_SLOT_6_START )
155 #define KMIN_SYS_CLOCK ( KMIN_SYS_ASIC + IOASIC_SLOT_8_START )
156 #define KMIN_SYS_SCSI ( KMIN_SYS_ASIC + IOASIC_SLOT_12_START )
157 #define KMIN_SYS_SCSI_DMA ( KMIN_SYS_ASIC + IOASIC_SLOT_14_START )
158 #define KMIN_SYS_BOOT_ROM_START ( KMIN_PHYS_TC_3_START + 0x3c00000 )
159 #define KMIN_SYS_BOOT_ROM_END ( KMIN_PHYS_TC_3_START + 0x3c40000 )
160 
161 /*
162  * Interrupts
163  */
164 #define KMIN_INT_FPA IP_LEV7 /* Floating Point coproc */
165 #define KMIN_INT_HALTB IP_LEV6 /* Halt button */
166 #define KMIN_INT_TC3 IP_LEV5 /* TC slot 3, system */
167 #define KMIN_INT_TC2 IP_LEV4 /* TC option slot 2 */
168 #define KMIN_INT_TC1 IP_LEV3 /* TC option slot 1 */
169 #define KMIN_INT_TC0 IP_LEV2 /* TC option slot 0 */
170 
171 /*
172  * System registers addresses (MREG and CREG space, and IO Control ASIC)
173  */
174 #define KMIN_REG_MER 0x0c400000 /* Memory error register */
175 #define KMIN_REG_MSR 0x0c800000 /* Memory size register */
176 
177 #define KMIN_REG_CNFG 0x0e000000 /* Config mem timeouts */
178 #define KMIN_REG_AER 0x0e000004 /* Address error register */
179 #define KMIN_REG_BOOT 0x0e000008 /* Boot 0 register */
180 #define KMIN_REG_TIMEOUT 0x0e00000c /* Mem access timeout reg */
181 
182 #define KMIN_REG_SCSI_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_DMAPTR )
183 #define KMIN_REG_SCSI_DMANPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_NEXTPTR )
184 #define KMIN_REG_LANCE_DMAPTR ( KMIN_SYS_ASIC + IOASIC_LANCE_DMAPTR )
185 #define KMIN_REG_SCC_T1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T1_DMAPTR )
186 #define KMIN_REG_SCC_R1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R1_DMAPTR )
187 #define KMIN_REG_SCC_T2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T2_DMAPTR )
188 #define KMIN_REG_SCC_R2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R2_DMAPTR )
189 #define KMIN_REG_CSR ( KMIN_SYS_ASIC + IOASIC_CSR )
190 #define KMIN_REG_INTR ( KMIN_SYS_ASIC + IOASIC_INTR )
191 #define KMIN_REG_IMSK ( KMIN_SYS_ASIC + IOASIC_IMSK )
192 #define KMIN_REG_CURADDR ( KMIN_SYS_ASIC + IOASIC_CURADDR )
193 
194 #define KMIN_REG_LANCE_DECODE ( KMIN_SYS_ASIC + IOASIC_LANCE_DECODE )
195 #define KMIN_REG_SCSI_DECODE ( KMIN_SYS_ASIC + IOASIC_SCSI_DECODE )
196 #define KMIN_REG_SCC0_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC0_DECODE )
197 #define KMIN_REG_SCC1_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC1_DECODE )
198 # define KMIN_LANCE_CONFIG 3
199 # define KMIN_SCSI_CONFIG 14
200 # define KMIN_SCC0_CONFIG (0x10|4)
201 # define KMIN_SCC1_CONFIG (0x10|6)
202 
203 #define KMIN_REG_SCSI_SCR ( KMIN_SYS_ASIC + IOASIC_SCSI_SCR )
204 #define KMIN_REG_SCSI_SDR0 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR0 )
205 #define KMIN_REG_SCSI_SDR1 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR1 )
206 
207 
208 /*
209  * System registers defines (MREG and CREG)
210  */
211 /* Memory error register */
212 #define KMIN_MER_xxx 0xfffe30ff /* undefined */
213 #define KMIN_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */
214 #define KMIN_MER_TLEN 0x00008000 /* rw: Xfer length error */
215 #define KMIN_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */
216 #define KMIN_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */
217 # define KMIN_LASTB31 0x00000800 /* upper byte of word */
218 # define KMIN_LASTB23 0x00000400 /* .. through .. */
219 # define KMIN_LASTB15 0x00000200 /* .. the .. */
220 # define KMIN_LASTB07 0x00000100 /* .. lower byte */
221 
222 /* Memory size register */
223 #define KMIN_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */
224 #define KMIN_MSR_xxx 0xffffdfff /* undefined */
225 
226 /* NOTES
227 
228  Memory access priority is, from higher to lower:
229  - DRAM refresh
230  - IO DMA (IO Control ASIC)
231  - Processor
232  - Slot 2 DMA
233  - Slot 1 DMA
234  - Slot 0 DMA
235 
236  Memory performance is (with 80ns mem cycles)
237  - single word read 5 cyc 10.0 Mb/s
238  - word write 3 cyc 16.7 Mb/s
239  - single byte write 3 cyc 4.2 Mb/s
240  - 64w DMA read 68 cyc 47.1 Mb/s
241  - 64w DMA write 66 cyc 48.5 Mb/s
242  - Refresh 5 cyc N/A
243  */
244 
245 /* Timeout config register */
246 #define KMIN_CNFG_VALUE_12Mhz 127
247 #define KMIN_CNFG_VALUE_25Mhz 0
248 
249 /* Address error register */
250 #define KMIN_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */
251 
252 /* Boot 0 register */
253 #define KMIN_BOOT_FROM_SLOT0 0x00000001 /* rw: diag board boot */
254 
255 /* Memory access timeout interrupt register */
256 #define KMIN_TIMEO_INTR 0x00000001 /* rc: intr pending */
257 
258 /*
259  * More system registers defines (IOASIC)
260  */
261 /* (re)defines for the system Status and Control register (SSR) */
262 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
263 #define KMIN_CSR_DIAGDN 0x00008000 /* rw */
264 #define KMIN_CSR_TXDIS_2 0x00004000 /* rw */
265 #define KMIN_CSR_TXDIS_1 0x00002000 /* rw */
266 #define KMIN_CSR_SCC_ENABLE 0x00000800 /* rw */
267 #define KMIN_CSR_RTC_ENABLE 0x00000400 /* rw */
268 #define KMIN_CSR_SCSI_ENABLE 0x00000200 /* rw */
269 #define KMIN_CSR_LANCE_ENABLE 0x00000100 /* rw */
270 #define KMIN_CSR_LEDS 0x000000ff /* rw */
271 
272 /* (re)defines for the System Interrupt and Mask Registers */
273 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
274 #define KMIN_INTR_NVR_JUMPER 0x00004000 /* ro */
275 #define KMIN_INTR_TIMEOUT 0x00001000 /* ro */
276 #define KMIN_INTR_NRMOD_JUMPER 0x00000400 /* ro */
277 #define KMIN_INTR_SCSI 0x00000200 /* ro */
278 #define KMIN_INTR_LANCE 0x00000100 /* ro */
279 #define KMIN_INTR_SCC_1 0x00000080 /* ro */
280 #define KMIN_INTR_SCC_0 0x00000040 /* ro */
281 #define KMIN_INTR_CLOCK 0x00000020 /* ro */
282 #define KMIN_INTR_PSWARN 0x00000010 /* ro */
283 #define KMIN_INTR_SCSI_FIFO 0x00000004 /* ro */
284 #define KMIN_INTR_PBNC 0x00000002 /* ro */
285 #define KMIN_INTR_PBNO 0x00000001 /* ro */
286 #define KMIN_INTR_ASIC 0xff0f0004
287 #define KMIN_IM0 0xff0f13f0 /* all good ones enabled */
288 
289 #endif /* MIPS_KMIN_H */
tc_ioasicreg.h

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