clmpccreg.h File Reference

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Macros
clmpccreg.h File Reference

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Macros

#define CLMPCC_FIFO_DEPTH   16
 
#define CLMPCC_REG_GFRCR   0x81 /* Global Firmware Revision Code Register */
 
#define CLMPCC_REG_CAR   0xee /* Channel Access Register */
 
#define CLMPCC_REG_CMR   0x1b /* Channel Mode Register */
 
#define CLMPCC_REG_COR1   0x10 /* Channel Option Register #1 */
 
#define CLMPCC_REG_COR2   0x17 /* Channel Option Register #2 */
 
#define CLMPCC_REG_COR3   0x16 /* Channel Option Register #3 */
 
#define CLMPCC_REG_COR4   0x15 /* Channel Option Register #4 */
 
#define CLMPCC_REG_COR5   0x14 /* Channel Option Register #5 */
 
#define CLMPCC_REG_COR6   0x18 /* Channel Option Register #6 */
 
#define CLMPCC_REG_COR7   0x07 /* Channel Option Register #7 */
 
#define CLMPCC_REG_SCHR1   0x1f /* Special Character Register #1 */
 
#define CLMPCC_REG_SCHR2   0x1e /* Special Character Register #2 */
 
#define CLMPCC_REG_SCHR3   0x1d /* Special Character Register #3 */
 
#define CLMPCC_REG_SCHR4   0x1c /* Special Character Register #4 */
 
#define CLMPCC_REG_SCRl   0x23 /* Special Character Range (low) */
 
#define CLMPCC_REG_SCRh   0x22 /* Special Character Range (high) */
 
#define CLMPCC_REG_LNXT   0x2e /* LNext Character */
 
#define CLMPCC_REG_RFAR1   0x1f /* Receive Frame Address Register #1 */
 
#define CLMPCC_REG_RFAR2   0x1e /* Receive Frame Address Register #2 */
 
#define CLMPCC_REG_RFAR3   0x1d /* Receive Frame Address Register #3 */
 
#define CLMPCC_REG_RFAR4   0x1c /* Receive Frame Address Register #4 */
 
#define CLMPCC_REG_CPSR   0xd6 /* CRC Polynomial Select Register */
 
#define CLMPCC_REG_RBPR   0xcb /* Receive Baud Rate Period Register */
 
#define CLMPCC_REG_RCOR   0xc8 /* Receive Clock Options Register */
 
#define CLMPCC_REG_TBPR   0xc3 /* Transmit Baud Rate Period Register */
 
#define CLMPCC_REG_TCOR   0xc0 /* Transmit Clock Options Register */
 
#define CLMPCC_REG_CCR   0x13 /* Channel Command Register */
 
#define CLMPCC_REG_STCR   0x12 /* Special Transmit Command Register */
 
#define CLMPCC_REG_CSR   0x1a /* Channel Status Register */
 
#define CLMPCC_REG_MSVR   0xde /* Modem Signal Value Register */
 
#define CLMPCC_REG_MSVR_RTS   0xde /* Modem Signal Value Register (RTS) */
 
#define CLMPCC_REG_MSVR_DTR   0xdf /* Modem Signal Value Register (DTR) */
 
#define CLMPCC_REG_LIVR   0x09 /* Local Interrupt Vector Register */
 
#define CLMPCC_REG_IER   0x11 /* Interrupt Enable Register */
 
#define CLMPCC_REG_LICR   0x26 /* Local Interrupting Channel Register */
 
#define CLMPCC_REG_STK   0xe2 /* Stack Register */
 
#define CLMPCC_REG_RPILR   0xe1 /* Receive Priority Interrupt Level Reg */
 
#define CLMPCC_REG_RIR   0xed /* Receive Interrupt Register */
 
#define CLMPCC_REG_RISR   0x88 /* Receive Interrupt Status Reg (16-bits) */
 
#define CLMPCC_REG_RISRl   0x89 /* Receive Interrupt Status Reg (low) */
 
#define CLMPCC_REG_RISRh   0x88 /* Receive Interrupt Status Reg (high) */
 
#define CLMPCC_REG_RFOC   0x30 /* Receive FIFO Output Count */
 
#define CLMPCC_REG_RDR   0xf8 /* Receive Data Register */
 
#define CLMPCC_REG_REOIR   0x84 /* Receive End of Interrupt Register */
 
#define CLMPCC_REG_TPILR   0xe0 /* Transmit Priority Interrupt Level Reg */
 
#define CLMPCC_REG_TIR   0xec /* Transmit Interrupt Register */
 
#define CLMPCC_REG_TISR   0x8a /* Transmit Interrupt Status Register */
 
#define CLMPCC_REG_TFTC   0x80 /* Transmit FIFO Transfer Count */
 
#define CLMPCC_REG_TDR   0xf8 /* Transmit Data Register */
 
#define CLMPCC_REG_TEOIR   0x85 /* Transmit End of Interrupt Register */
 
#define CLMPCC_REG_MPILR   0xe3 /* Modem Priority Interrupt Level Reg */
 
#define CLMPCC_REG_MIR   0xef /* Modem Interrupt Register */
 
#define CLMPCC_REG_MISR   0x8b /* Modem (/Timer) Interrupt Status Reg */
 
#define CLMPCC_REG_MEOIR   0x86 /* Modem End of Interrupt Register */
 
#define CLMPCC_REG_DMR   0xf6 /* DMA Mode Register (write only) */
 
#define CLMPCC_REG_BERCNT   0x8e /* Bus Error Retry Count */
 
#define CLMPCC_REG_DMABSTS   0x19 /* DMA Buffer Status */
 
#define CLMPCC_REG_ARBADRL   0x42 /* A Receive Buffer Address Lower (word) */
 
#define CLMPCC_REG_ARBADRU   0x40 /* A Receive Buffer Address Upper (word) */
 
#define CLMPCC_REG_BRBADRL   0x46 /* B Receive Buffer Address Lower (word) */
 
#define CLMPCC_REG_BRBADRU   0x44 /* B Receive Buffer Address Upper (16bit) */
 
#define CLMPCC_REG_ARBCNT   0x4a /* A Receive Buffer Byte Count (word) */
 
#define CLMPCC_REG_BRBCNT   0x48 /* B Receive Buffer Byte Count (word) */
 
#define CLMPCC_REG_ARBSTS   0x4f /* A Receive Buffer Status */
 
#define CLMPCC_REG_BRBSTS   0x4e /* B Receive Buffer Status */
 
#define CLMPCC_REG_RCBADRL   0x3e /* Receive Current Buff Addr Lower (word) */
 
#define CLMPCC_REG_RCBADRU   0x3c /* Receive Current Buff Addr Upper (word) */
 
#define CLMPCC_REG_ATBADRL   0x52 /* A Transmit Buffer Address Lower (word) */
 
#define CLMPCC_REG_ATBADRU   0x50 /* A Transmit Buffer Address Upper (word) */
 
#define CLMPCC_REG_BTBADRL   0x56 /* B Transmit Buffer Address Lower (word) */
 
#define CLMPCC_REG_BTBADRU   0x54 /* B Transmit Buffer Address Upper (word) */
 
#define CLMPCC_REG_ATBCNT   0x5a /* A Transmit Buffer Byte Count (word) */
 
#define CLMPCC_REG_BTBCNT   0x58 /* B Transmit Buffer Byte Count (word) */
 
#define CLMPCC_REG_ATBSTS   0x5f /* A Transmit Buffer Status */
 
#define CLMPCC_REG_BTBSTS   0x5e /* B Transmit Buffer Status */
 
#define CLMPCC_REG_TCBADRL   0x3a /* Transmit Current Buf Addr Lower (word) */
 
#define CLMPCC_REG_TCBADRU   0x38 /* Transmit Current Buf Addr Upper (word) */
 
#define CLMPCC_REG_TPR   0xda /* Timer Period Register */
 
#define CLMPCC_REG_RTPR   0x24 /* Receive Timeout Period Register (word) */
 
#define CLMPCC_REG_RTPRl   0x25 /* Receive Timeout Period Register (low) */
 
#define CLMPCC_REG_RTPRh   0x24 /* Receive Timeout Period Register (high) */
 
#define CLMPCC_REG_GT1   0x2a /* General Timer 1 (word) */
 
#define CLMPCC_REG_GT1l   0x2b /* General Timer 1 (low) */
 
#define CLMPCC_REG_GT1h   0x2a /* General Timer 1 (high) */
 
#define CLMPCC_REG_GT2   0x29 /* General Timer 2 */
 
#define CLMPCC_REG_TTR   0x29 /* Transmit Timer Register */
 
#define CLMPCC_CAR_MASK   0x03 /* Channel bit mask */
 
#define CLMPCC_CMR_RX_INT   (0 << 7) /* Rx using interrupts */
 
#define CLMPCC_CMR_RX_DMA   (1 << 7) /* Rx using DMA */
 
#define CLMPCC_CMR_TX_INT   (0 << 6) /* Tx using interrupts */
 
#define CLMPCC_CMR_TX_DMA   (1 << 6) /* Tx using DMA */
 
#define CLMPCC_CMR_HDLC   0x00 /* Select HDLC mode */
 
#define CLMPCC_CMR_BISYNC   0x01 /* Select Bisync mode */
 
#define CLMPCC_CMR_ASYNC   0x02 /* Select async mode */
 
#define CLMPCC_CMR_X21   0x03 /* Select X.21 mode */
 
#define CLMPCC_COR1_EVEN_PARITY   (0 << 7) /* Even parity */
 
#define CLMPCC_COR1_ODD_PARITY   (1 << 7) /* Odd parity */
 
#define CLMPCC_COR1_NO_PARITY   (0 << 5) /* No parity */
 
#define CLMPCC_COR1_FORCE_PAR   (1 << 5) /* Force parity */
 
#define CLMPCC_COR1_NORM_PARITY   (2 << 5) /* Normal parity */
 
#define CLMPCC_COR1_CHECK_PAR   (0 << 4) /* Check parity */
 
#define CLMPCC_COR1_IGNORE_PAR   (1 << 4) /* Ignore parity */
 
#define CLMPCC_COR1_CHAR_5BITS   0x04 /* 5 bits per character */
 
#define CLMPCC_COR1_CHAR_6BITS   0x05 /* 6 bits per character */
 
#define CLMPCC_COR1_CHAR_7BITS   0x06 /* 7 bits per character */
 
#define CLMPCC_COR1_CHAR_8BITS   0x07 /* 8 bits per character */
 
#define CLMPCC_COR2_IXM   (1 << 7) /* Implied XON mode */
 
#define CLMPCC_COR2_TxIBE   (1 << 6) /* Transmit In-Band Flow Control */
 
#define CLMPCC_COR2_ETC   (1 << 5) /* Embedded Tx Command Enable */
 
#define CLMPCC_COR2_RLM   (1 << 3) /* Remote Loopback Mode */
 
#define CLMPCC_COR2_RtsAO   (1 << 2) /* RTS Automatic Output Enable */
 
#define CLMPCC_COR2_CtsAE   (1 << 1) /* CTS Automatic Enable */
 
#define CLMPCC_COR2_DsrAE   (1 << 1) /* DSR Automatic Enable */
 
#define CLMPCC_ETC_MAGIC   0x00 /* Introduces a command */
 
#define CLMPCC_ETC_SEND_BREAK   0x81 /* Send a BREAK character */
 
#define CLMPCC_ETC_DELAY   0x82 /* Insert a delay */
 
#define CLMPCC_ETC_STOP_BREAK   0x83 /* Stop sending BREAK */
 
#define CLMPCC_COR3_ESCDE   (1 << 7) /* Ext Special Char Detect Enab */
 
#define CLMPCC_COR3_RngDE   (1 << 6) /* Range Detect Enable */
 
#define CLMPCC_COR3_FCT   (1 << 5) /* Flow Ctrl Transparency Mode */
 
#define CLMPCC_COR3_SCDE   (1 << 4) /* Special Character Detection */
 
#define CLMPCC_COR3_SpIstp   (1 << 3) /* Special Character I Strip */
 
#define CLMPCC_COR3_STOP_1   0x02 /* 1 Stop Bit */
 
#define CLMPCC_COR3_STOP_1_5   0x03 /* 1.5 Stop Bits */
 
#define CLMPCC_COR3_STOP_2   0x04 /* 2 Stop Bits */
 
#define CLMPCC_COR4_DSRzd   (1 << 7) /* Detect 1->0 transition on DSR */
 
#define CLMPCC_COR4_CDzd   (1 << 6) /* Detect 1->0 transition on CD */
 
#define CLMPCC_COR4_CTSzd   (1 << 5) /* Detect 1->0 transition on CTS */
 
#define CLMPCC_COR4_FIFO_MASK   0x0f /* FIFO Threshold bits */
 
#define CLMPCC_COR4_FIFO_LOW   1
 
#define CLMPCC_COR4_FIFO_MED   4
 
#define CLMPCC_COR4_FIFO_HIGH   8
 
#define CLMPCC_COR5_DSRod   (1 << 7) /* Detect 0->1 transition on DSR */
 
#define CLMPCC_COR5_CDod   (1 << 6) /* Detect 0->1 transition on CD */
 
#define CLMPCC_COR5_CTSod   (1 << 5) /* Detect 0->1 transition on CTS */
 
#define CLMPCC_COR5_FLOW_MASK   0x0f /* Rx Flow Control FIFO Threshold */
 
#define CLMPCC_COR5_FLOW_NORM   8
 
#define CLMPCC_COR6_RX_CRNL   0x00 /* No special action on CR or NL */
 
#define CLMPCC_COR6_BRK_EXCEPT   (0 << 3) /* Exception interrupt on BREAK */
 
#define CLMPCC_COR6_BRK_2_NULL   (1 << 3) /* Translate BREAK to NULL char */
 
#define CLMPCC_COR6_BRK_DISCARD   (3 << 3) /* Discard BREAK characters */
 
#define CLMPCC_COR6_PF_EXCEPT   0x00 /* Exception irq on parity/frame */
 
#define CLMPCC_COR6_PF_2_NULL   0x01 /* Translate parity/frame to NULL */
 
#define CLMPCC_COR6_PF_IGNORE   0x02 /* Ignore error */
 
#define CLMPCC_COR6_PF_DISCARD   0x03 /* Discard character */
 
#define CLMPCC_COR6_PF_TRANS   0x05 /* Translate to FF NULL + char */
 
#define CLMPCC_COR7_ISTRIP   (1 << 7) /* Strip MSB */
 
#define CLMPCC_COR7_LNE   (1 << 6) /* Enable LNext Option */
 
#define CLMPCC_COR7_FCERR   (1 << 5) /* Flow Control on Error Char */
 
#define CLMPCC_COR7_TX_CRNL   0x00 /* No special action on NL or CR */
 
#define CLMPCC_RCOR_CLK(x)   (x)
 
#define CLMPCC_RCOR_TLVAL   (1 << 7) /* Transmit Line Value */
 
#define CLMPCC_RCOR_DPLL_ENABLE   (1 << 5) /* Phase Locked Loop Enable */
 
#define CLMPCC_RCOR_DPLL_NRZ   (0 << 3) /* PLL runs in NRZ mode */
 
#define CLMPCC_RCOR_DPLL_NRZI   (1 << 3) /* PLL runs in NRZI mode */
 
#define CLMPCC_RCOR_DPLL_MAN   (2 << 3) /* PLL runs in Manchester mode */
 
#define CLMPCC_RCOR_CLK_0   0x0 /* Rx Clock Source 'Clk0' */
 
#define CLMPCC_RCOR_CLK_1   0x1 /* Rx Clock Source 'Clk1' */
 
#define CLMPCC_RCOR_CLK_2   0x2 /* Rx Clock Source 'Clk2' */
 
#define CLMPCC_RCOR_CLK_3   0x3 /* Rx Clock Source 'Clk3' */
 
#define CLMPCC_RCOR_CLK_4   0x4 /* Rx Clock Source 'Clk4' */
 
#define CLMPCC_RCOR_CLK_EXT   0x6 /* Rx Clock Source 'External' */
 
#define CLMPCC_TCOR_CLK(x)   ((x) << 5)
 
#define CLMPCC_TCOR_CLK_0   (0 << 5) /* Tx Clock Source 'Clk0' */
 
#define CLMPCC_TCOR_CLK_1   (1 << 5) /* Tx Clock Source 'Clk1' */
 
#define CLMPCC_TCOR_CLK_2   (2 << 5) /* Tx Clock Source 'Clk2' */
 
#define CLMPCC_TCOR_CLK_3   (3 << 5) /* Tx Clock Source 'Clk3' */
 
#define CLMPCC_TCOR_CLK_4   (4 << 5) /* Tx Clock Source 'Clk4' */
 
#define CLMPCC_TCOR_CLK_EXT   (6 << 5) /* Tx Clock Source 'External' */
 
#define CLMPCC_TCOR_CLK_RX   (7 << 5) /* Tx Clock Source 'Same as Rx' */
 
#define CLMPCC_TCOR_EXT_1X   (1 << 3) /* Times 1 External Clock */
 
#define CLMPCC_TCOR_LOCAL_LOOP   (1 << 1) /* Enable Local Loopback */
 
#define CLMPCC_STCR_SSPC(n)   ((n) & 0x7) /* Send special character 'n' */
 
#define CLMPCC_STCR_SND_SPC   (1 << 3) /* Initiate send special char */
 
#define CLMPCC_STCR_APPEND_COMP   (1 << 5) /* Append complete (Async DMA) */
 
#define CLMPCC_STCR_ABORT_TX   (1 << 6) /* Abort Tx (HDLC Mode only) */
 
#define CLMPCC_CCR_T0_CLEAR   0x40 /* Type 0: Clear Channel */
 
#define CLMPCC_CCR_T0_INIT   0x20 /* Type 0: Initialise Channel */
 
#define CLMPCC_CCR_T0_RESET_ALL   0x10 /* Type 0: Reset All */
 
#define CLMPCC_CCR_T0_TX_EN   0x08 /* Type 0: Transmitter Enable */
 
#define CLMPCC_CCR_T0_TX_DIS   0x04 /* Type 0: Transmitter Disable */
 
#define CLMPCC_CCR_T0_RX_EN   0x02 /* Type 0: Receiver Enable */
 
#define CLMPCC_CCR_T0_RX_DIS   0x01 /* Type 0: Receiver Disable */
 
#define CLMPCC_CCR_T1_CLR_TMR1   0xc0 /* Type 1: Clear Timer 1 */
 
#define CLMPCC_CCR_T1_CLR_TMR2   0xa0 /* Type 1: Clear Timer 5 */
 
#define CLMPCC_CCR_T1_CLR_RECV   0x90 /* Type 1: Clear Receiver */
 
#define CLMPCC_CSR_RX_ENABLED   (1 << 7) /* Receiver Enabled */
 
#define CLMPCC_CSR_RX_FLOW_OFF   (1 << 6) /* Receive Flow Off */
 
#define CLMPCC_CSR_RX_FLOW_ON   (1 << 5) /* Receive Flow On */
 
#define CLMPCC_CSR_TX_ENABLED   (1 << 3) /* Transmitter Enabled */
 
#define CLMPCC_CSR_TX_FLOW_OFF   (1 << 2) /* Transmit Flow Off */
 
#define CLMPCC_CSR_TX_FLOW_ON   (1 << 1) /* Transmit Flow On */
 
#define CLMPCC_MSVR_DSR   (1 << 7) /* Current State of DSR Input */
 
#define CLMPCC_MSVR_CD   (1 << 6) /* Current State of CD Input */
 
#define CLMPCC_MSVR_CTS   (1 << 5) /* Current State of CTS Input */
 
#define CLMPCC_MSVR_DTR_OPT   (1 << 4) /* DTR Option Select */
 
#define CLMPCC_MSVR_PORT_ID   (1 << 2) /* Device Type (2400 / 2401) */
 
#define CLMPCC_MSVR_DTR   (1 << 1) /* Current State of DTR Output */
 
#define CLMPCC_MSVR_RTS   (1 << 0) /* Current State of RTS Output */
 
#define CLMPCC_LIVR_TYPE_MASK   0x03 /* Type of Interrupt */
 
#define CLMPCC_LIVR_EXCEPTION   0x0 /* Exception (DMA Completion) */
 
#define CLMPCC_LIVR_MODEM   0x1 /* Modem Signal Change */
 
#define CLMPCC_LIVR_TX   0x2 /* Transmit Data Interrupt */
 
#define CLMPCC_LIVR_RX   0x3 /* Receive Data Interrupt */
 
#define CLMPCC_IER_MODEM   (1 << 7) /* Modem Pin Change Detect */
 
#define CLMPCC_IER_RET   (1 << 5) /* Receive Exception Timeout */
 
#define CLMPCC_IER_RX_FIFO   (1 << 3) /* Rx FIFO Threshold Reached */
 
#define CLMPCC_IER_TIMER   (1 << 2) /* General Timer(s) Timeout */
 
#define CLMPCC_IER_TX_EMPTY   (1 << 1) /* Tx Empty */
 
#define CLMPCC_IER_TX_FIFO   (1 << 0) /* Tx FIFO Threshold Reached */
 
#define CLMPCC_LICR_MASK   0x0c /* Mask for channel number */
 
#define CLMPCC_LICR_CHAN(v)   (((v) & CLMPCC_LICR_MASK) >> 2)
 
#define CLMPCC_RIR_REN   (1 << 7) /* Receive Enable */
 
#define CLMPCC_RIR_RACT   (1 << 6) /* Receive Active */
 
#define CLMPCC_RIR_REOI   (1 << 5) /* Receive End of Interrupt */
 
#define CLMPCC_RIR_RCVT_MASK   0x0c
 
#define CLMPCC_RIR_RCN_MASK   0x03
 
#define CLMPCC_RISR_TIMEOUT   (1 << 7) /* Rx FIFO Empty and Timeout */
 
#define CLMPCC_RISR_OVERRUN   (1 << 3) /* Rx Overrun Error */
 
#define CLMPCC_RISR_PARITY   (1 << 2) /* Rx Parity Error */
 
#define CLMPCC_RISR_FRAMING   (1 << 1) /* Rx Framing Error */
 
#define CLMPCC_RISR_BREAK   (1 << 0) /* BREAK Detected */
 
#define CLMPCC_RFOC_MASK   0x1f /* Mask for valid bits */
 
#define CLMPCC_REOIR_TERMBUFF   (1 << 7) /* Terminate Current DMA Buffer */
 
#define CLMPCC_REOIR_DIS_EX_CHR   (1 << 6) /* Discard Exception Char (DMA) */
 
#define CLMPCC_REOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */
 
#define CLMPCC_REOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */
 
#define CLMPCC_REOIR_NO_TRANS   (1 << 3) /* No Transfer of Data */
 
#define CLMPCC_TIR_TEN   (1 << 7) /* Transmit Enable */
 
#define CLMPCC_TIR_TACT   (1 << 6) /* Transmit Active */
 
#define CLMPCC_TIR_TEOI   (1 << 5) /* Transmit End of Interrupt */
 
#define CLMPCC_TIR_TCVT_MASK   0x0c
 
#define CLMPCC_TIR_TCN_MASK   0x03
 
#define CLMPCC_TISR_BERR   (1 << 7) /* Bus Error (DMA) */
 
#define CLMPCC_TISR_EOF   (1 << 6) /* Transmit End of Frame (DMA) */
 
#define CLMPCC_TISR_EOB   (1 << 5) /* Transmit End of Buffer (DMA) */
 
#define CLMPCC_TISR_UNDERRUN   (1 << 4) /* Transmit Underrun (sync only) */
 
#define CLMPCC_TISR_BUFF_ID   (1 << 3) /* Buffer that has exception */
 
#define CLMPCC_TISR_TX_EMPTY   (1 << 1) /* Transmitter Empty */
 
#define CLMPCC_TISR_TX_FIFO   (1 << 0) /* Transmit FIFO Below Threshold */
 
#define CLMPCC_TFTC_MASK   0x1f /* Mask for valid bits */
 
#define CLMPCC_TEOIR_TERMBUFF   (1 << 7) /* Terminate Current DMA Buffer */
 
#define CLMPCC_TEOIR_END_OF_FRM   (1 << 6) /* End of Frame (sync mode) */
 
#define CLMPCC_TEOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */
 
#define CLMPCC_TEOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */
 
#define CLMPCC_TEOIR_NO_TRANS   (1 << 3) /* No Transfer of Data */
 
#define CLMPCC_MIR_MEN   (1 << 7) /* Modem Enable */
 
#define CLMPCC_MIR_MACT   (1 << 6) /* Modem Active */
 
#define CLMPCC_MIR_MEOI   (1 << 5) /* Modem End of Interrupt */
 
#define CLMPCC_MIR_MCVT_MASK   0x0c
 
#define CLMPCC_MIR_MCN_MASK   0x03
 
#define CLMPCC_MISR_DSR   (1 << 7) /* DSR Changed State */
 
#define CLMPCC_MISR_CD   (1 << 6) /* CD Changed State */
 
#define CLMPCC_MISR_CTS   (1 << 5) /* CTS Changed State */
 
#define CLMPCC_MISR_TMR2   (1 << 1) /* Timer 2 Timed Out */
 
#define CLMPCC_MISR_TMR1   (1 << 0) /* Timer 1 Timed Out */
 
#define CLMPCC_MEOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */
 
#define CLMPCC_MEOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */
 
#define CLMPCC_RTPR_DEFAULT   2 /* 2mS timeout period */
 
#define CLMPCC_MSEC_TO_TPR(c, m)
 

Macro Definition Documentation

◆ CLMPCC_CAR_MASK

#define CLMPCC_CAR_MASK   0x03 /* Channel bit mask */

Definition at line 174 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_CLEAR

#define CLMPCC_CCR_T0_CLEAR   0x40 /* Type 0: Clear Channel */

Definition at line 290 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_INIT

#define CLMPCC_CCR_T0_INIT   0x20 /* Type 0: Initialise Channel */

Definition at line 291 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_RESET_ALL

#define CLMPCC_CCR_T0_RESET_ALL   0x10 /* Type 0: Reset All */

Definition at line 292 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_RX_DIS

#define CLMPCC_CCR_T0_RX_DIS   0x01 /* Type 0: Receiver Disable */

Definition at line 296 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_RX_EN

#define CLMPCC_CCR_T0_RX_EN   0x02 /* Type 0: Receiver Enable */

Definition at line 295 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_TX_DIS

#define CLMPCC_CCR_T0_TX_DIS   0x04 /* Type 0: Transmitter Disable */

Definition at line 294 of file clmpccreg.h.

◆ CLMPCC_CCR_T0_TX_EN

#define CLMPCC_CCR_T0_TX_EN   0x08 /* Type 0: Transmitter Enable */

Definition at line 293 of file clmpccreg.h.

◆ CLMPCC_CCR_T1_CLR_RECV

#define CLMPCC_CCR_T1_CLR_RECV   0x90 /* Type 1: Clear Receiver */

Definition at line 299 of file clmpccreg.h.

◆ CLMPCC_CCR_T1_CLR_TMR1

#define CLMPCC_CCR_T1_CLR_TMR1   0xc0 /* Type 1: Clear Timer 1 */

Definition at line 297 of file clmpccreg.h.

◆ CLMPCC_CCR_T1_CLR_TMR2

#define CLMPCC_CCR_T1_CLR_TMR2   0xa0 /* Type 1: Clear Timer 5 */

Definition at line 298 of file clmpccreg.h.

◆ CLMPCC_CMR_ASYNC

#define CLMPCC_CMR_ASYNC   0x02 /* Select async mode */

Definition at line 183 of file clmpccreg.h.

◆ CLMPCC_CMR_BISYNC

#define CLMPCC_CMR_BISYNC   0x01 /* Select Bisync mode */

Definition at line 182 of file clmpccreg.h.

◆ CLMPCC_CMR_HDLC

#define CLMPCC_CMR_HDLC   0x00 /* Select HDLC mode */

Definition at line 181 of file clmpccreg.h.

◆ CLMPCC_CMR_RX_DMA

#define CLMPCC_CMR_RX_DMA   (1 << 7) /* Rx using DMA */

Definition at line 178 of file clmpccreg.h.

◆ CLMPCC_CMR_RX_INT

#define CLMPCC_CMR_RX_INT   (0 << 7) /* Rx using interrupts */

Definition at line 177 of file clmpccreg.h.

◆ CLMPCC_CMR_TX_DMA

#define CLMPCC_CMR_TX_DMA   (1 << 6) /* Tx using DMA */

Definition at line 180 of file clmpccreg.h.

◆ CLMPCC_CMR_TX_INT

#define CLMPCC_CMR_TX_INT   (0 << 6) /* Tx using interrupts */

Definition at line 179 of file clmpccreg.h.

◆ CLMPCC_CMR_X21

#define CLMPCC_CMR_X21   0x03 /* Select X.21 mode */

Definition at line 184 of file clmpccreg.h.

◆ CLMPCC_COR1_CHAR_5BITS

#define CLMPCC_COR1_CHAR_5BITS   0x04 /* 5 bits per character */

Definition at line 194 of file clmpccreg.h.

◆ CLMPCC_COR1_CHAR_6BITS

#define CLMPCC_COR1_CHAR_6BITS   0x05 /* 6 bits per character */

Definition at line 195 of file clmpccreg.h.

◆ CLMPCC_COR1_CHAR_7BITS

#define CLMPCC_COR1_CHAR_7BITS   0x06 /* 7 bits per character */

Definition at line 196 of file clmpccreg.h.

◆ CLMPCC_COR1_CHAR_8BITS

#define CLMPCC_COR1_CHAR_8BITS   0x07 /* 8 bits per character */

Definition at line 197 of file clmpccreg.h.

◆ CLMPCC_COR1_CHECK_PAR

#define CLMPCC_COR1_CHECK_PAR   (0 << 4) /* Check parity */

Definition at line 192 of file clmpccreg.h.

◆ CLMPCC_COR1_EVEN_PARITY

#define CLMPCC_COR1_EVEN_PARITY   (0 << 7) /* Even parity */

Definition at line 187 of file clmpccreg.h.

◆ CLMPCC_COR1_FORCE_PAR

#define CLMPCC_COR1_FORCE_PAR   (1 << 5) /* Force parity */

Definition at line 190 of file clmpccreg.h.

◆ CLMPCC_COR1_IGNORE_PAR

#define CLMPCC_COR1_IGNORE_PAR   (1 << 4) /* Ignore parity */

Definition at line 193 of file clmpccreg.h.

◆ CLMPCC_COR1_NO_PARITY

#define CLMPCC_COR1_NO_PARITY   (0 << 5) /* No parity */

Definition at line 189 of file clmpccreg.h.

◆ CLMPCC_COR1_NORM_PARITY

#define CLMPCC_COR1_NORM_PARITY   (2 << 5) /* Normal parity */

Definition at line 191 of file clmpccreg.h.

◆ CLMPCC_COR1_ODD_PARITY

#define CLMPCC_COR1_ODD_PARITY   (1 << 7) /* Odd parity */

Definition at line 188 of file clmpccreg.h.

◆ CLMPCC_COR2_CtsAE

#define CLMPCC_COR2_CtsAE   (1 << 1) /* CTS Automatic Enable */

Definition at line 205 of file clmpccreg.h.

◆ CLMPCC_COR2_DsrAE

#define CLMPCC_COR2_DsrAE   (1 << 1) /* DSR Automatic Enable */

Definition at line 206 of file clmpccreg.h.

◆ CLMPCC_COR2_ETC

#define CLMPCC_COR2_ETC   (1 << 5) /* Embedded Tx Command Enable */

Definition at line 202 of file clmpccreg.h.

◆ CLMPCC_COR2_IXM

#define CLMPCC_COR2_IXM   (1 << 7) /* Implied XON mode */

Definition at line 200 of file clmpccreg.h.

◆ CLMPCC_COR2_RLM

#define CLMPCC_COR2_RLM   (1 << 3) /* Remote Loopback Mode */

Definition at line 203 of file clmpccreg.h.

◆ CLMPCC_COR2_RtsAO

#define CLMPCC_COR2_RtsAO   (1 << 2) /* RTS Automatic Output Enable */

Definition at line 204 of file clmpccreg.h.

◆ CLMPCC_COR2_TxIBE

#define CLMPCC_COR2_TxIBE   (1 << 6) /* Transmit In-Band Flow Control */

Definition at line 201 of file clmpccreg.h.

◆ CLMPCC_COR3_ESCDE

#define CLMPCC_COR3_ESCDE   (1 << 7) /* Ext Special Char Detect Enab */

Definition at line 215 of file clmpccreg.h.

◆ CLMPCC_COR3_FCT

#define CLMPCC_COR3_FCT   (1 << 5) /* Flow Ctrl Transparency Mode */

Definition at line 217 of file clmpccreg.h.

◆ CLMPCC_COR3_RngDE

#define CLMPCC_COR3_RngDE   (1 << 6) /* Range Detect Enable */

Definition at line 216 of file clmpccreg.h.

◆ CLMPCC_COR3_SCDE

#define CLMPCC_COR3_SCDE   (1 << 4) /* Special Character Detection */

Definition at line 218 of file clmpccreg.h.

◆ CLMPCC_COR3_SpIstp

#define CLMPCC_COR3_SpIstp   (1 << 3) /* Special Character I Strip */

Definition at line 219 of file clmpccreg.h.

◆ CLMPCC_COR3_STOP_1

#define CLMPCC_COR3_STOP_1   0x02 /* 1 Stop Bit */

Definition at line 220 of file clmpccreg.h.

◆ CLMPCC_COR3_STOP_1_5

#define CLMPCC_COR3_STOP_1_5   0x03 /* 1.5 Stop Bits */

Definition at line 221 of file clmpccreg.h.

◆ CLMPCC_COR3_STOP_2

#define CLMPCC_COR3_STOP_2   0x04 /* 2 Stop Bits */

Definition at line 222 of file clmpccreg.h.

◆ CLMPCC_COR4_CDzd

#define CLMPCC_COR4_CDzd   (1 << 6) /* Detect 1->0 transition on CD */

Definition at line 226 of file clmpccreg.h.

◆ CLMPCC_COR4_CTSzd

#define CLMPCC_COR4_CTSzd   (1 << 5) /* Detect 1->0 transition on CTS */

Definition at line 227 of file clmpccreg.h.

◆ CLMPCC_COR4_DSRzd

#define CLMPCC_COR4_DSRzd   (1 << 7) /* Detect 1->0 transition on DSR */

Definition at line 225 of file clmpccreg.h.

◆ CLMPCC_COR4_FIFO_HIGH

#define CLMPCC_COR4_FIFO_HIGH   8

Definition at line 231 of file clmpccreg.h.

◆ CLMPCC_COR4_FIFO_LOW

#define CLMPCC_COR4_FIFO_LOW   1

Definition at line 229 of file clmpccreg.h.

◆ CLMPCC_COR4_FIFO_MASK

#define CLMPCC_COR4_FIFO_MASK   0x0f /* FIFO Threshold bits */

Definition at line 228 of file clmpccreg.h.

◆ CLMPCC_COR4_FIFO_MED

#define CLMPCC_COR4_FIFO_MED   4

Definition at line 230 of file clmpccreg.h.

◆ CLMPCC_COR5_CDod

#define CLMPCC_COR5_CDod   (1 << 6) /* Detect 0->1 transition on CD */

Definition at line 235 of file clmpccreg.h.

◆ CLMPCC_COR5_CTSod

#define CLMPCC_COR5_CTSod   (1 << 5) /* Detect 0->1 transition on CTS */

Definition at line 236 of file clmpccreg.h.

◆ CLMPCC_COR5_DSRod

#define CLMPCC_COR5_DSRod   (1 << 7) /* Detect 0->1 transition on DSR */

Definition at line 234 of file clmpccreg.h.

◆ CLMPCC_COR5_FLOW_MASK

#define CLMPCC_COR5_FLOW_MASK   0x0f /* Rx Flow Control FIFO Threshold */

Definition at line 237 of file clmpccreg.h.

◆ CLMPCC_COR5_FLOW_NORM

#define CLMPCC_COR5_FLOW_NORM   8

Definition at line 238 of file clmpccreg.h.

◆ CLMPCC_COR6_BRK_2_NULL

#define CLMPCC_COR6_BRK_2_NULL   (1 << 3) /* Translate BREAK to NULL char */

Definition at line 243 of file clmpccreg.h.

◆ CLMPCC_COR6_BRK_DISCARD

#define CLMPCC_COR6_BRK_DISCARD   (3 << 3) /* Discard BREAK characters */

Definition at line 244 of file clmpccreg.h.

◆ CLMPCC_COR6_BRK_EXCEPT

#define CLMPCC_COR6_BRK_EXCEPT   (0 << 3) /* Exception interrupt on BREAK */

Definition at line 242 of file clmpccreg.h.

◆ CLMPCC_COR6_PF_2_NULL

#define CLMPCC_COR6_PF_2_NULL   0x01 /* Translate parity/frame to NULL */

Definition at line 246 of file clmpccreg.h.

◆ CLMPCC_COR6_PF_DISCARD

#define CLMPCC_COR6_PF_DISCARD   0x03 /* Discard character */

Definition at line 248 of file clmpccreg.h.

◆ CLMPCC_COR6_PF_EXCEPT

#define CLMPCC_COR6_PF_EXCEPT   0x00 /* Exception irq on parity/frame */

Definition at line 245 of file clmpccreg.h.

◆ CLMPCC_COR6_PF_IGNORE

#define CLMPCC_COR6_PF_IGNORE   0x02 /* Ignore error */

Definition at line 247 of file clmpccreg.h.

◆ CLMPCC_COR6_PF_TRANS

#define CLMPCC_COR6_PF_TRANS   0x05 /* Translate to FF NULL + char */

Definition at line 249 of file clmpccreg.h.

◆ CLMPCC_COR6_RX_CRNL

#define CLMPCC_COR6_RX_CRNL   0x00 /* No special action on CR or NL */

Definition at line 241 of file clmpccreg.h.

◆ CLMPCC_COR7_FCERR

#define CLMPCC_COR7_FCERR   (1 << 5) /* Flow Control on Error Char */

Definition at line 254 of file clmpccreg.h.

◆ CLMPCC_COR7_ISTRIP

#define CLMPCC_COR7_ISTRIP   (1 << 7) /* Strip MSB */

Definition at line 252 of file clmpccreg.h.

◆ CLMPCC_COR7_LNE

#define CLMPCC_COR7_LNE   (1 << 6) /* Enable LNext Option */

Definition at line 253 of file clmpccreg.h.

◆ CLMPCC_COR7_TX_CRNL

#define CLMPCC_COR7_TX_CRNL   0x00 /* No special action on NL or CR */

Definition at line 255 of file clmpccreg.h.

◆ CLMPCC_CSR_RX_ENABLED

#define CLMPCC_CSR_RX_ENABLED   (1 << 7) /* Receiver Enabled */

Definition at line 302 of file clmpccreg.h.

◆ CLMPCC_CSR_RX_FLOW_OFF

#define CLMPCC_CSR_RX_FLOW_OFF   (1 << 6) /* Receive Flow Off */

Definition at line 303 of file clmpccreg.h.

◆ CLMPCC_CSR_RX_FLOW_ON

#define CLMPCC_CSR_RX_FLOW_ON   (1 << 5) /* Receive Flow On */

Definition at line 304 of file clmpccreg.h.

◆ CLMPCC_CSR_TX_ENABLED

#define CLMPCC_CSR_TX_ENABLED   (1 << 3) /* Transmitter Enabled */

Definition at line 305 of file clmpccreg.h.

◆ CLMPCC_CSR_TX_FLOW_OFF

#define CLMPCC_CSR_TX_FLOW_OFF   (1 << 2) /* Transmit Flow Off */

Definition at line 306 of file clmpccreg.h.

◆ CLMPCC_CSR_TX_FLOW_ON

#define CLMPCC_CSR_TX_FLOW_ON   (1 << 1) /* Transmit Flow On */

Definition at line 307 of file clmpccreg.h.

◆ CLMPCC_ETC_DELAY

#define CLMPCC_ETC_DELAY   0x82 /* Insert a delay */

Definition at line 211 of file clmpccreg.h.

◆ CLMPCC_ETC_MAGIC

#define CLMPCC_ETC_MAGIC   0x00 /* Introduces a command */

Definition at line 209 of file clmpccreg.h.

◆ CLMPCC_ETC_SEND_BREAK

#define CLMPCC_ETC_SEND_BREAK   0x81 /* Send a BREAK character */

Definition at line 210 of file clmpccreg.h.

◆ CLMPCC_ETC_STOP_BREAK

#define CLMPCC_ETC_STOP_BREAK   0x83 /* Stop sending BREAK */

Definition at line 212 of file clmpccreg.h.

◆ CLMPCC_FIFO_DEPTH

#define CLMPCC_FIFO_DEPTH   16

Definition at line 60 of file clmpccreg.h.

◆ CLMPCC_IER_MODEM

#define CLMPCC_IER_MODEM   (1 << 7) /* Modem Pin Change Detect */

Definition at line 326 of file clmpccreg.h.

◆ CLMPCC_IER_RET

#define CLMPCC_IER_RET   (1 << 5) /* Receive Exception Timeout */

Definition at line 327 of file clmpccreg.h.

◆ CLMPCC_IER_RX_FIFO

#define CLMPCC_IER_RX_FIFO   (1 << 3) /* Rx FIFO Threshold Reached */

Definition at line 328 of file clmpccreg.h.

◆ CLMPCC_IER_TIMER

#define CLMPCC_IER_TIMER   (1 << 2) /* General Timer(s) Timeout */

Definition at line 329 of file clmpccreg.h.

◆ CLMPCC_IER_TX_EMPTY

#define CLMPCC_IER_TX_EMPTY   (1 << 1) /* Tx Empty */

Definition at line 330 of file clmpccreg.h.

◆ CLMPCC_IER_TX_FIFO

#define CLMPCC_IER_TX_FIFO   (1 << 0) /* Tx FIFO Threshold Reached */

Definition at line 331 of file clmpccreg.h.

◆ CLMPCC_LICR_CHAN

#define CLMPCC_LICR_CHAN (   v)    (((v) & CLMPCC_LICR_MASK) >> 2)

Definition at line 335 of file clmpccreg.h.

◆ CLMPCC_LICR_MASK

#define CLMPCC_LICR_MASK   0x0c /* Mask for channel number */

Definition at line 334 of file clmpccreg.h.

◆ CLMPCC_LIVR_EXCEPTION

#define CLMPCC_LIVR_EXCEPTION   0x0 /* Exception (DMA Completion) */

Definition at line 320 of file clmpccreg.h.

◆ CLMPCC_LIVR_MODEM

#define CLMPCC_LIVR_MODEM   0x1 /* Modem Signal Change */

Definition at line 321 of file clmpccreg.h.

◆ CLMPCC_LIVR_RX

#define CLMPCC_LIVR_RX   0x3 /* Receive Data Interrupt */

Definition at line 323 of file clmpccreg.h.

◆ CLMPCC_LIVR_TX

#define CLMPCC_LIVR_TX   0x2 /* Transmit Data Interrupt */

Definition at line 322 of file clmpccreg.h.

◆ CLMPCC_LIVR_TYPE_MASK

#define CLMPCC_LIVR_TYPE_MASK   0x03 /* Type of Interrupt */

Definition at line 319 of file clmpccreg.h.

◆ CLMPCC_MEOIR_TMR1_SYNC

#define CLMPCC_MEOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */

Definition at line 403 of file clmpccreg.h.

◆ CLMPCC_MEOIR_TMR2_SYNC

#define CLMPCC_MEOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */

Definition at line 402 of file clmpccreg.h.

◆ CLMPCC_MIR_MACT

#define CLMPCC_MIR_MACT   (1 << 6) /* Modem Active */

Definition at line 389 of file clmpccreg.h.

◆ CLMPCC_MIR_MCN_MASK

#define CLMPCC_MIR_MCN_MASK   0x03

Definition at line 392 of file clmpccreg.h.

◆ CLMPCC_MIR_MCVT_MASK

#define CLMPCC_MIR_MCVT_MASK   0x0c

Definition at line 391 of file clmpccreg.h.

◆ CLMPCC_MIR_MEN

#define CLMPCC_MIR_MEN   (1 << 7) /* Modem Enable */

Definition at line 388 of file clmpccreg.h.

◆ CLMPCC_MIR_MEOI

#define CLMPCC_MIR_MEOI   (1 << 5) /* Modem End of Interrupt */

Definition at line 390 of file clmpccreg.h.

◆ CLMPCC_MISR_CD

#define CLMPCC_MISR_CD   (1 << 6) /* CD Changed State */

Definition at line 396 of file clmpccreg.h.

◆ CLMPCC_MISR_CTS

#define CLMPCC_MISR_CTS   (1 << 5) /* CTS Changed State */

Definition at line 397 of file clmpccreg.h.

◆ CLMPCC_MISR_DSR

#define CLMPCC_MISR_DSR   (1 << 7) /* DSR Changed State */

Definition at line 395 of file clmpccreg.h.

◆ CLMPCC_MISR_TMR1

#define CLMPCC_MISR_TMR1   (1 << 0) /* Timer 1 Timed Out */

Definition at line 399 of file clmpccreg.h.

◆ CLMPCC_MISR_TMR2

#define CLMPCC_MISR_TMR2   (1 << 1) /* Timer 2 Timed Out */

Definition at line 398 of file clmpccreg.h.

◆ CLMPCC_MSEC_TO_TPR

#define CLMPCC_MSEC_TO_TPR (   c,
 
)
Value:
(((((c)/2048)/(1000/(m))) > 0x0a) ? \
(((c)/2048)/(1000/(m))) : 0x0a)

Definition at line 413 of file clmpccreg.h.

◆ CLMPCC_MSVR_CD

#define CLMPCC_MSVR_CD   (1 << 6) /* Current State of CD Input */

Definition at line 311 of file clmpccreg.h.

◆ CLMPCC_MSVR_CTS

#define CLMPCC_MSVR_CTS   (1 << 5) /* Current State of CTS Input */

Definition at line 312 of file clmpccreg.h.

◆ CLMPCC_MSVR_DSR

#define CLMPCC_MSVR_DSR   (1 << 7) /* Current State of DSR Input */

Definition at line 310 of file clmpccreg.h.

◆ CLMPCC_MSVR_DTR

#define CLMPCC_MSVR_DTR   (1 << 1) /* Current State of DTR Output */

Definition at line 315 of file clmpccreg.h.

◆ CLMPCC_MSVR_DTR_OPT

#define CLMPCC_MSVR_DTR_OPT   (1 << 4) /* DTR Option Select */

Definition at line 313 of file clmpccreg.h.

◆ CLMPCC_MSVR_PORT_ID

#define CLMPCC_MSVR_PORT_ID   (1 << 2) /* Device Type (2400 / 2401) */

Definition at line 314 of file clmpccreg.h.

◆ CLMPCC_MSVR_RTS

#define CLMPCC_MSVR_RTS   (1 << 0) /* Current State of RTS Output */

Definition at line 316 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK

#define CLMPCC_RCOR_CLK (   x)    (x)

Definition at line 258 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_0

#define CLMPCC_RCOR_CLK_0   0x0 /* Rx Clock Source 'Clk0' */

Definition at line 264 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_1

#define CLMPCC_RCOR_CLK_1   0x1 /* Rx Clock Source 'Clk1' */

Definition at line 265 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_2

#define CLMPCC_RCOR_CLK_2   0x2 /* Rx Clock Source 'Clk2' */

Definition at line 266 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_3

#define CLMPCC_RCOR_CLK_3   0x3 /* Rx Clock Source 'Clk3' */

Definition at line 267 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_4

#define CLMPCC_RCOR_CLK_4   0x4 /* Rx Clock Source 'Clk4' */

Definition at line 268 of file clmpccreg.h.

◆ CLMPCC_RCOR_CLK_EXT

#define CLMPCC_RCOR_CLK_EXT   0x6 /* Rx Clock Source 'External' */

Definition at line 269 of file clmpccreg.h.

◆ CLMPCC_RCOR_DPLL_ENABLE

#define CLMPCC_RCOR_DPLL_ENABLE   (1 << 5) /* Phase Locked Loop Enable */

Definition at line 260 of file clmpccreg.h.

◆ CLMPCC_RCOR_DPLL_MAN

#define CLMPCC_RCOR_DPLL_MAN   (2 << 3) /* PLL runs in Manchester mode */

Definition at line 263 of file clmpccreg.h.

◆ CLMPCC_RCOR_DPLL_NRZ

#define CLMPCC_RCOR_DPLL_NRZ   (0 << 3) /* PLL runs in NRZ mode */

Definition at line 261 of file clmpccreg.h.

◆ CLMPCC_RCOR_DPLL_NRZI

#define CLMPCC_RCOR_DPLL_NRZI   (1 << 3) /* PLL runs in NRZI mode */

Definition at line 262 of file clmpccreg.h.

◆ CLMPCC_RCOR_TLVAL

#define CLMPCC_RCOR_TLVAL   (1 << 7) /* Transmit Line Value */

Definition at line 259 of file clmpccreg.h.

◆ CLMPCC_REG_ARBADRL

#define CLMPCC_REG_ARBADRL   0x42 /* A Receive Buffer Address Lower (word) */

Definition at line 138 of file clmpccreg.h.

◆ CLMPCC_REG_ARBADRU

#define CLMPCC_REG_ARBADRU   0x40 /* A Receive Buffer Address Upper (word) */

Definition at line 139 of file clmpccreg.h.

◆ CLMPCC_REG_ARBCNT

#define CLMPCC_REG_ARBCNT   0x4a /* A Receive Buffer Byte Count (word) */

Definition at line 142 of file clmpccreg.h.

◆ CLMPCC_REG_ARBSTS

#define CLMPCC_REG_ARBSTS   0x4f /* A Receive Buffer Status */

Definition at line 144 of file clmpccreg.h.

◆ CLMPCC_REG_ATBADRL

#define CLMPCC_REG_ATBADRL   0x52 /* A Transmit Buffer Address Lower (word) */

Definition at line 150 of file clmpccreg.h.

◆ CLMPCC_REG_ATBADRU

#define CLMPCC_REG_ATBADRU   0x50 /* A Transmit Buffer Address Upper (word) */

Definition at line 151 of file clmpccreg.h.

◆ CLMPCC_REG_ATBCNT

#define CLMPCC_REG_ATBCNT   0x5a /* A Transmit Buffer Byte Count (word) */

Definition at line 154 of file clmpccreg.h.

◆ CLMPCC_REG_ATBSTS

#define CLMPCC_REG_ATBSTS   0x5f /* A Transmit Buffer Status */

Definition at line 156 of file clmpccreg.h.

◆ CLMPCC_REG_BERCNT

#define CLMPCC_REG_BERCNT   0x8e /* Bus Error Retry Count */

Definition at line 134 of file clmpccreg.h.

◆ CLMPCC_REG_BRBADRL

#define CLMPCC_REG_BRBADRL   0x46 /* B Receive Buffer Address Lower (word) */

Definition at line 140 of file clmpccreg.h.

◆ CLMPCC_REG_BRBADRU

#define CLMPCC_REG_BRBADRU   0x44 /* B Receive Buffer Address Upper (16bit) */

Definition at line 141 of file clmpccreg.h.

◆ CLMPCC_REG_BRBCNT

#define CLMPCC_REG_BRBCNT   0x48 /* B Receive Buffer Byte Count (word) */

Definition at line 143 of file clmpccreg.h.

◆ CLMPCC_REG_BRBSTS

#define CLMPCC_REG_BRBSTS   0x4e /* B Receive Buffer Status */

Definition at line 145 of file clmpccreg.h.

◆ CLMPCC_REG_BTBADRL

#define CLMPCC_REG_BTBADRL   0x56 /* B Transmit Buffer Address Lower (word) */

Definition at line 152 of file clmpccreg.h.

◆ CLMPCC_REG_BTBADRU

#define CLMPCC_REG_BTBADRU   0x54 /* B Transmit Buffer Address Upper (word) */

Definition at line 153 of file clmpccreg.h.

◆ CLMPCC_REG_BTBCNT

#define CLMPCC_REG_BTBCNT   0x58 /* B Transmit Buffer Byte Count (word) */

Definition at line 155 of file clmpccreg.h.

◆ CLMPCC_REG_BTBSTS

#define CLMPCC_REG_BTBSTS   0x5e /* B Transmit Buffer Status */

Definition at line 157 of file clmpccreg.h.

◆ CLMPCC_REG_CAR

#define CLMPCC_REG_CAR   0xee /* Channel Access Register */

Definition at line 64 of file clmpccreg.h.

◆ CLMPCC_REG_CCR

#define CLMPCC_REG_CCR   0x13 /* Channel Command Register */

Definition at line 95 of file clmpccreg.h.

◆ CLMPCC_REG_CMR

#define CLMPCC_REG_CMR   0x1b /* Channel Mode Register */

Definition at line 67 of file clmpccreg.h.

◆ CLMPCC_REG_COR1

#define CLMPCC_REG_COR1   0x10 /* Channel Option Register #1 */

Definition at line 68 of file clmpccreg.h.

◆ CLMPCC_REG_COR2

#define CLMPCC_REG_COR2   0x17 /* Channel Option Register #2 */

Definition at line 69 of file clmpccreg.h.

◆ CLMPCC_REG_COR3

#define CLMPCC_REG_COR3   0x16 /* Channel Option Register #3 */

Definition at line 70 of file clmpccreg.h.

◆ CLMPCC_REG_COR4

#define CLMPCC_REG_COR4   0x15 /* Channel Option Register #4 */

Definition at line 71 of file clmpccreg.h.

◆ CLMPCC_REG_COR5

#define CLMPCC_REG_COR5   0x14 /* Channel Option Register #5 */

Definition at line 72 of file clmpccreg.h.

◆ CLMPCC_REG_COR6

#define CLMPCC_REG_COR6   0x18 /* Channel Option Register #6 */

Definition at line 73 of file clmpccreg.h.

◆ CLMPCC_REG_COR7

#define CLMPCC_REG_COR7   0x07 /* Channel Option Register #7 */

Definition at line 74 of file clmpccreg.h.

◆ CLMPCC_REG_CPSR

#define CLMPCC_REG_CPSR   0xd6 /* CRC Polynomial Select Register */

Definition at line 86 of file clmpccreg.h.

◆ CLMPCC_REG_CSR

#define CLMPCC_REG_CSR   0x1a /* Channel Status Register */

Definition at line 97 of file clmpccreg.h.

◆ CLMPCC_REG_DMABSTS

#define CLMPCC_REG_DMABSTS   0x19 /* DMA Buffer Status */

Definition at line 135 of file clmpccreg.h.

◆ CLMPCC_REG_DMR

#define CLMPCC_REG_DMR   0xf6 /* DMA Mode Register (write only) */

Definition at line 133 of file clmpccreg.h.

◆ CLMPCC_REG_GFRCR

#define CLMPCC_REG_GFRCR   0x81 /* Global Firmware Revision Code Register */

Definition at line 63 of file clmpccreg.h.

◆ CLMPCC_REG_GT1

#define CLMPCC_REG_GT1   0x2a /* General Timer 1 (word) */

Definition at line 166 of file clmpccreg.h.

◆ CLMPCC_REG_GT1h

#define CLMPCC_REG_GT1h   0x2a /* General Timer 1 (high) */

Definition at line 168 of file clmpccreg.h.

◆ CLMPCC_REG_GT1l

#define CLMPCC_REG_GT1l   0x2b /* General Timer 1 (low) */

Definition at line 167 of file clmpccreg.h.

◆ CLMPCC_REG_GT2

#define CLMPCC_REG_GT2   0x29 /* General Timer 2 */

Definition at line 169 of file clmpccreg.h.

◆ CLMPCC_REG_IER

#define CLMPCC_REG_IER   0x11 /* Interrupt Enable Register */

Definition at line 104 of file clmpccreg.h.

◆ CLMPCC_REG_LICR

#define CLMPCC_REG_LICR   0x26 /* Local Interrupting Channel Register */

Definition at line 105 of file clmpccreg.h.

◆ CLMPCC_REG_LIVR

#define CLMPCC_REG_LIVR   0x09 /* Local Interrupt Vector Register */

Definition at line 103 of file clmpccreg.h.

◆ CLMPCC_REG_LNXT

#define CLMPCC_REG_LNXT   0x2e /* LNext Character */

Definition at line 81 of file clmpccreg.h.

◆ CLMPCC_REG_MEOIR

#define CLMPCC_REG_MEOIR   0x86 /* Modem End of Interrupt Register */

Definition at line 130 of file clmpccreg.h.

◆ CLMPCC_REG_MIR

#define CLMPCC_REG_MIR   0xef /* Modem Interrupt Register */

Definition at line 128 of file clmpccreg.h.

◆ CLMPCC_REG_MISR

#define CLMPCC_REG_MISR   0x8b /* Modem (/Timer) Interrupt Status Reg */

Definition at line 129 of file clmpccreg.h.

◆ CLMPCC_REG_MPILR

#define CLMPCC_REG_MPILR   0xe3 /* Modem Priority Interrupt Level Reg */

Definition at line 127 of file clmpccreg.h.

◆ CLMPCC_REG_MSVR

#define CLMPCC_REG_MSVR   0xde /* Modem Signal Value Register */

Definition at line 98 of file clmpccreg.h.

◆ CLMPCC_REG_MSVR_DTR

#define CLMPCC_REG_MSVR_DTR   0xdf /* Modem Signal Value Register (DTR) */

Definition at line 100 of file clmpccreg.h.

◆ CLMPCC_REG_MSVR_RTS

#define CLMPCC_REG_MSVR_RTS   0xde /* Modem Signal Value Register (RTS) */

Definition at line 99 of file clmpccreg.h.

◆ CLMPCC_REG_RBPR

#define CLMPCC_REG_RBPR   0xcb /* Receive Baud Rate Period Register */

Definition at line 89 of file clmpccreg.h.

◆ CLMPCC_REG_RCBADRL

#define CLMPCC_REG_RCBADRL   0x3e /* Receive Current Buff Addr Lower (word) */

Definition at line 146 of file clmpccreg.h.

◆ CLMPCC_REG_RCBADRU

#define CLMPCC_REG_RCBADRU   0x3c /* Receive Current Buff Addr Upper (word) */

Definition at line 147 of file clmpccreg.h.

◆ CLMPCC_REG_RCOR

#define CLMPCC_REG_RCOR   0xc8 /* Receive Clock Options Register */

Definition at line 90 of file clmpccreg.h.

◆ CLMPCC_REG_RDR

#define CLMPCC_REG_RDR   0xf8 /* Receive Data Register */

Definition at line 115 of file clmpccreg.h.

◆ CLMPCC_REG_REOIR

#define CLMPCC_REG_REOIR   0x84 /* Receive End of Interrupt Register */

Definition at line 116 of file clmpccreg.h.

◆ CLMPCC_REG_RFAR1

#define CLMPCC_REG_RFAR1   0x1f /* Receive Frame Address Register #1 */

Definition at line 82 of file clmpccreg.h.

◆ CLMPCC_REG_RFAR2

#define CLMPCC_REG_RFAR2   0x1e /* Receive Frame Address Register #2 */

Definition at line 83 of file clmpccreg.h.

◆ CLMPCC_REG_RFAR3

#define CLMPCC_REG_RFAR3   0x1d /* Receive Frame Address Register #3 */

Definition at line 84 of file clmpccreg.h.

◆ CLMPCC_REG_RFAR4

#define CLMPCC_REG_RFAR4   0x1c /* Receive Frame Address Register #4 */

Definition at line 85 of file clmpccreg.h.

◆ CLMPCC_REG_RFOC

#define CLMPCC_REG_RFOC   0x30 /* Receive FIFO Output Count */

Definition at line 114 of file clmpccreg.h.

◆ CLMPCC_REG_RIR

#define CLMPCC_REG_RIR   0xed /* Receive Interrupt Register */

Definition at line 110 of file clmpccreg.h.

◆ CLMPCC_REG_RISR

#define CLMPCC_REG_RISR   0x88 /* Receive Interrupt Status Reg (16-bits) */

Definition at line 111 of file clmpccreg.h.

◆ CLMPCC_REG_RISRh

#define CLMPCC_REG_RISRh   0x88 /* Receive Interrupt Status Reg (high) */

Definition at line 113 of file clmpccreg.h.

◆ CLMPCC_REG_RISRl

#define CLMPCC_REG_RISRl   0x89 /* Receive Interrupt Status Reg (low) */

Definition at line 112 of file clmpccreg.h.

◆ CLMPCC_REG_RPILR

#define CLMPCC_REG_RPILR   0xe1 /* Receive Priority Interrupt Level Reg */

Definition at line 109 of file clmpccreg.h.

◆ CLMPCC_REG_RTPR

#define CLMPCC_REG_RTPR   0x24 /* Receive Timeout Period Register (word) */

Definition at line 163 of file clmpccreg.h.

◆ CLMPCC_REG_RTPRh

#define CLMPCC_REG_RTPRh   0x24 /* Receive Timeout Period Register (high) */

Definition at line 165 of file clmpccreg.h.

◆ CLMPCC_REG_RTPRl

#define CLMPCC_REG_RTPRl   0x25 /* Receive Timeout Period Register (low) */

Definition at line 164 of file clmpccreg.h.

◆ CLMPCC_REG_SCHR1

#define CLMPCC_REG_SCHR1   0x1f /* Special Character Register #1 */

Definition at line 75 of file clmpccreg.h.

◆ CLMPCC_REG_SCHR2

#define CLMPCC_REG_SCHR2   0x1e /* Special Character Register #2 */

Definition at line 76 of file clmpccreg.h.

◆ CLMPCC_REG_SCHR3

#define CLMPCC_REG_SCHR3   0x1d /* Special Character Register #3 */

Definition at line 77 of file clmpccreg.h.

◆ CLMPCC_REG_SCHR4

#define CLMPCC_REG_SCHR4   0x1c /* Special Character Register #4 */

Definition at line 78 of file clmpccreg.h.

◆ CLMPCC_REG_SCRh

#define CLMPCC_REG_SCRh   0x22 /* Special Character Range (high) */

Definition at line 80 of file clmpccreg.h.

◆ CLMPCC_REG_SCRl

#define CLMPCC_REG_SCRl   0x23 /* Special Character Range (low) */

Definition at line 79 of file clmpccreg.h.

◆ CLMPCC_REG_STCR

#define CLMPCC_REG_STCR   0x12 /* Special Transmit Command Register */

Definition at line 96 of file clmpccreg.h.

◆ CLMPCC_REG_STK

#define CLMPCC_REG_STK   0xe2 /* Stack Register */

Definition at line 106 of file clmpccreg.h.

◆ CLMPCC_REG_TBPR

#define CLMPCC_REG_TBPR   0xc3 /* Transmit Baud Rate Period Register */

Definition at line 91 of file clmpccreg.h.

◆ CLMPCC_REG_TCBADRL

#define CLMPCC_REG_TCBADRL   0x3a /* Transmit Current Buf Addr Lower (word) */

Definition at line 158 of file clmpccreg.h.

◆ CLMPCC_REG_TCBADRU

#define CLMPCC_REG_TCBADRU   0x38 /* Transmit Current Buf Addr Upper (word) */

Definition at line 159 of file clmpccreg.h.

◆ CLMPCC_REG_TCOR

#define CLMPCC_REG_TCOR   0xc0 /* Transmit Clock Options Register */

Definition at line 92 of file clmpccreg.h.

◆ CLMPCC_REG_TDR

#define CLMPCC_REG_TDR   0xf8 /* Transmit Data Register */

Definition at line 123 of file clmpccreg.h.

◆ CLMPCC_REG_TEOIR

#define CLMPCC_REG_TEOIR   0x85 /* Transmit End of Interrupt Register */

Definition at line 124 of file clmpccreg.h.

◆ CLMPCC_REG_TFTC

#define CLMPCC_REG_TFTC   0x80 /* Transmit FIFO Transfer Count */

Definition at line 122 of file clmpccreg.h.

◆ CLMPCC_REG_TIR

#define CLMPCC_REG_TIR   0xec /* Transmit Interrupt Register */

Definition at line 120 of file clmpccreg.h.

◆ CLMPCC_REG_TISR

#define CLMPCC_REG_TISR   0x8a /* Transmit Interrupt Status Register */

Definition at line 121 of file clmpccreg.h.

◆ CLMPCC_REG_TPILR

#define CLMPCC_REG_TPILR   0xe0 /* Transmit Priority Interrupt Level Reg */

Definition at line 119 of file clmpccreg.h.

◆ CLMPCC_REG_TPR

#define CLMPCC_REG_TPR   0xda /* Timer Period Register */

Definition at line 162 of file clmpccreg.h.

◆ CLMPCC_REG_TTR

#define CLMPCC_REG_TTR   0x29 /* Transmit Timer Register */

Definition at line 170 of file clmpccreg.h.

◆ CLMPCC_REOIR_DIS_EX_CHR

#define CLMPCC_REOIR_DIS_EX_CHR   (1 << 6) /* Discard Exception Char (DMA) */

Definition at line 356 of file clmpccreg.h.

◆ CLMPCC_REOIR_NO_TRANS

#define CLMPCC_REOIR_NO_TRANS   (1 << 3) /* No Transfer of Data */

Definition at line 359 of file clmpccreg.h.

◆ CLMPCC_REOIR_TERMBUFF

#define CLMPCC_REOIR_TERMBUFF   (1 << 7) /* Terminate Current DMA Buffer */

Definition at line 355 of file clmpccreg.h.

◆ CLMPCC_REOIR_TMR1_SYNC

#define CLMPCC_REOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */

Definition at line 358 of file clmpccreg.h.

◆ CLMPCC_REOIR_TMR2_SYNC

#define CLMPCC_REOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */

Definition at line 357 of file clmpccreg.h.

◆ CLMPCC_RFOC_MASK

#define CLMPCC_RFOC_MASK   0x1f /* Mask for valid bits */

Definition at line 352 of file clmpccreg.h.

◆ CLMPCC_RIR_RACT

#define CLMPCC_RIR_RACT   (1 << 6) /* Receive Active */

Definition at line 339 of file clmpccreg.h.

◆ CLMPCC_RIR_RCN_MASK

#define CLMPCC_RIR_RCN_MASK   0x03

Definition at line 342 of file clmpccreg.h.

◆ CLMPCC_RIR_RCVT_MASK

#define CLMPCC_RIR_RCVT_MASK   0x0c

Definition at line 341 of file clmpccreg.h.

◆ CLMPCC_RIR_REN

#define CLMPCC_RIR_REN   (1 << 7) /* Receive Enable */

Definition at line 338 of file clmpccreg.h.

◆ CLMPCC_RIR_REOI

#define CLMPCC_RIR_REOI   (1 << 5) /* Receive End of Interrupt */

Definition at line 340 of file clmpccreg.h.

◆ CLMPCC_RISR_BREAK

#define CLMPCC_RISR_BREAK   (1 << 0) /* BREAK Detected */

Definition at line 349 of file clmpccreg.h.

◆ CLMPCC_RISR_FRAMING

#define CLMPCC_RISR_FRAMING   (1 << 1) /* Rx Framing Error */

Definition at line 348 of file clmpccreg.h.

◆ CLMPCC_RISR_OVERRUN

#define CLMPCC_RISR_OVERRUN   (1 << 3) /* Rx Overrun Error */

Definition at line 346 of file clmpccreg.h.

◆ CLMPCC_RISR_PARITY

#define CLMPCC_RISR_PARITY   (1 << 2) /* Rx Parity Error */

Definition at line 347 of file clmpccreg.h.

◆ CLMPCC_RISR_TIMEOUT

#define CLMPCC_RISR_TIMEOUT   (1 << 7) /* Rx FIFO Empty and Timeout */

Definition at line 345 of file clmpccreg.h.

◆ CLMPCC_RTPR_DEFAULT

#define CLMPCC_RTPR_DEFAULT   2 /* 2mS timeout period */

Definition at line 406 of file clmpccreg.h.

◆ CLMPCC_STCR_ABORT_TX

#define CLMPCC_STCR_ABORT_TX   (1 << 6) /* Abort Tx (HDLC Mode only) */

Definition at line 287 of file clmpccreg.h.

◆ CLMPCC_STCR_APPEND_COMP

#define CLMPCC_STCR_APPEND_COMP   (1 << 5) /* Append complete (Async DMA) */

Definition at line 286 of file clmpccreg.h.

◆ CLMPCC_STCR_SND_SPC

#define CLMPCC_STCR_SND_SPC   (1 << 3) /* Initiate send special char */

Definition at line 285 of file clmpccreg.h.

◆ CLMPCC_STCR_SSPC

#define CLMPCC_STCR_SSPC (   n)    ((n) & 0x7) /* Send special character 'n' */

Definition at line 284 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK

#define CLMPCC_TCOR_CLK (   x)    ((x) << 5)

Definition at line 272 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_0

#define CLMPCC_TCOR_CLK_0   (0 << 5) /* Tx Clock Source 'Clk0' */

Definition at line 273 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_1

#define CLMPCC_TCOR_CLK_1   (1 << 5) /* Tx Clock Source 'Clk1' */

Definition at line 274 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_2

#define CLMPCC_TCOR_CLK_2   (2 << 5) /* Tx Clock Source 'Clk2' */

Definition at line 275 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_3

#define CLMPCC_TCOR_CLK_3   (3 << 5) /* Tx Clock Source 'Clk3' */

Definition at line 276 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_4

#define CLMPCC_TCOR_CLK_4   (4 << 5) /* Tx Clock Source 'Clk4' */

Definition at line 277 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_EXT

#define CLMPCC_TCOR_CLK_EXT   (6 << 5) /* Tx Clock Source 'External' */

Definition at line 278 of file clmpccreg.h.

◆ CLMPCC_TCOR_CLK_RX

#define CLMPCC_TCOR_CLK_RX   (7 << 5) /* Tx Clock Source 'Same as Rx' */

Definition at line 279 of file clmpccreg.h.

◆ CLMPCC_TCOR_EXT_1X

#define CLMPCC_TCOR_EXT_1X   (1 << 3) /* Times 1 External Clock */

Definition at line 280 of file clmpccreg.h.

◆ CLMPCC_TCOR_LOCAL_LOOP

#define CLMPCC_TCOR_LOCAL_LOOP   (1 << 1) /* Enable Local Loopback */

Definition at line 281 of file clmpccreg.h.

◆ CLMPCC_TEOIR_END_OF_FRM

#define CLMPCC_TEOIR_END_OF_FRM   (1 << 6) /* End of Frame (sync mode) */

Definition at line 382 of file clmpccreg.h.

◆ CLMPCC_TEOIR_NO_TRANS

#define CLMPCC_TEOIR_NO_TRANS   (1 << 3) /* No Transfer of Data */

Definition at line 385 of file clmpccreg.h.

◆ CLMPCC_TEOIR_TERMBUFF

#define CLMPCC_TEOIR_TERMBUFF   (1 << 7) /* Terminate Current DMA Buffer */

Definition at line 381 of file clmpccreg.h.

◆ CLMPCC_TEOIR_TMR1_SYNC

#define CLMPCC_TEOIR_TMR1_SYNC   (1 << 4) /* Set Timer 1 in Sync Mode */

Definition at line 384 of file clmpccreg.h.

◆ CLMPCC_TEOIR_TMR2_SYNC

#define CLMPCC_TEOIR_TMR2_SYNC   (1 << 5) /* Set Timer 2 in Sync Mode */

Definition at line 383 of file clmpccreg.h.

◆ CLMPCC_TFTC_MASK

#define CLMPCC_TFTC_MASK   0x1f /* Mask for valid bits */

Definition at line 378 of file clmpccreg.h.

◆ CLMPCC_TIR_TACT

#define CLMPCC_TIR_TACT   (1 << 6) /* Transmit Active */

Definition at line 363 of file clmpccreg.h.

◆ CLMPCC_TIR_TCN_MASK

#define CLMPCC_TIR_TCN_MASK   0x03

Definition at line 366 of file clmpccreg.h.

◆ CLMPCC_TIR_TCVT_MASK

#define CLMPCC_TIR_TCVT_MASK   0x0c

Definition at line 365 of file clmpccreg.h.

◆ CLMPCC_TIR_TEN

#define CLMPCC_TIR_TEN   (1 << 7) /* Transmit Enable */

Definition at line 362 of file clmpccreg.h.

◆ CLMPCC_TIR_TEOI

#define CLMPCC_TIR_TEOI   (1 << 5) /* Transmit End of Interrupt */

Definition at line 364 of file clmpccreg.h.

◆ CLMPCC_TISR_BERR

#define CLMPCC_TISR_BERR   (1 << 7) /* Bus Error (DMA) */

Definition at line 369 of file clmpccreg.h.

◆ CLMPCC_TISR_BUFF_ID

#define CLMPCC_TISR_BUFF_ID   (1 << 3) /* Buffer that has exception */

Definition at line 373 of file clmpccreg.h.

◆ CLMPCC_TISR_EOB

#define CLMPCC_TISR_EOB   (1 << 5) /* Transmit End of Buffer (DMA) */

Definition at line 371 of file clmpccreg.h.

◆ CLMPCC_TISR_EOF

#define CLMPCC_TISR_EOF   (1 << 6) /* Transmit End of Frame (DMA) */

Definition at line 370 of file clmpccreg.h.

◆ CLMPCC_TISR_TX_EMPTY

#define CLMPCC_TISR_TX_EMPTY   (1 << 1) /* Transmitter Empty */

Definition at line 374 of file clmpccreg.h.

◆ CLMPCC_TISR_TX_FIFO

#define CLMPCC_TISR_TX_FIFO   (1 << 0) /* Transmit FIFO Below Threshold */

Definition at line 375 of file clmpccreg.h.

◆ CLMPCC_TISR_UNDERRUN

#define CLMPCC_TISR_UNDERRUN   (1 << 4) /* Transmit Underrun (sync only) */

Definition at line 372 of file clmpccreg.h.


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