vr_rtcreg.h Source File
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41 #define SECMIN ((unsigned)60)
42 #define SECHOUR ((unsigned)(60*SECMIN))
44 #define SEC2MIN ((unsigned)60/2)
45 #define SEC2HOUR ((unsigned)(60*SECMIN)/2)
46 #define SEC2DAY ((unsigned)(24*SECHOUR)/2)
47 #define SEC2YR ((unsigned)(365*SECDAY)/2)
59 #define EPOCHYEAR 1850
64 #define LEAPYEAR4(year) ((((year) % 4) == 0 && ((year) % 100) != 0) || ((year%400)) == 0)
65 #define LEAPYEAR2(year) (((year) % 4) == 0)
73 #define RTC_NO_REG_W 0xffffffff
75 #define ETIME_L_REG_W 0x000
76 #define ETIME_M_REG_W 0x002
77 #define ETIME_H_REG_W 0x004
79 #define ETIME_L_HZ 0x8000
82 #define ECMP_L_REG_W 0x008
83 #define ECMP_M_REG_W 0x00a
84 #define ECMP_H_REG_W 0x00c
87 #define RTCL1_L_REG_W 0x010
88 #define RTCL1_H_REG_W 0x012
90 #define RTCL1_L_HZ 0x8000
93 #define RTCL1_CNT_L_REG_W 0x014
94 #define RTCL1_CNT_H_REG_W 0x016
97 #define RTCL2_L_REG_W 0x018
98 #define RTCL2_H_REG_W 0x01a
100 #define RTCL2_L_HZ 0x8000
103 #define RTCL2_CNT_L_REG_W 0x01c
104 #define RTCL2_CNT_H_REG_W 0x01e
107 #define VR4102_TCLK_L_REG_W 0x100
108 #define VR4102_TCLK_H_REG_W 0x102
109 #define VR4122_TCLK_L_REG_W 0x020
110 #define VR4122_TCLK_H_REG_W 0x022
111 #if defined SINGLE_VRIP_BASE
112 #if defined VRGROUP_4102_4121
113 #define TCLK_L_REG_W VR4102_TCLK_L_REG_W
114 #define TCLK_H_REG_W VR4102_TCLK_H_REG_W
116 #if defined VRGROUP_4122_4131
117 #define TCLK_L_REG_W VR4122_TCLK_L_REG_W
118 #define TCLK_H_REG_W VR4122_TCLK_H_REG_W
120 #if defined VRGROUP_4181
121 #define TCLK_L_REG_W RTC_NO_REG_W
122 #define TCLK_H_REG_W RTC_NO_REG_W
127 #define VR4102_TCLK_CNT_L_REG_W 0x104
128 #define VR4102_TCLK_CNT_H_REG_W 0x106
129 #define VR4122_TCLK_CNT_L_REG_W 0x024
130 #define VR4122_TCLK_CNT_H_REG_W 0x026
131 #if defined SINGLE_VRIP_BASE
132 #if defined VRGROUP_4102_4121
133 #define TCLK_CNT_L_REG_W VR4102_TCLK_CNT_L_REG_W
134 #define TCLK_CNT_H_REG_W VR4102_TCLK_CNT_L_REG_W
136 #if defined VRGROUP_4122_4131
137 #define TCLK_CNT_L_REG_W VR4122_TCLK_CNT_L_REG_W
138 #define TCLK_CNT_H_REG_W VR4122_TCLK_CNT_H_REG_W
140 #if defined VRGROUP_4181
141 #define TCLK_CNT_L_REG_W RTC_NO_REG_W
142 #define TCLK_CNT_H_REG_W RTC_NO_REG_W
147 #define VR4102_RTCINT_REG_W 0x11e
148 #define VR4122_RTCINT_REG_W 0x03e
149 #define VR4181_RTCINT_REG_W 0x11e
150 #if defined SINGLE_VRIP_BASE
151 #if defined VRGROUP_4102_4121
152 #define RTCINT_REG_W VR4102_RTCINT_REG_W
154 #if defined VRGROUP_4122_4131
155 #define RTCINT_REG_W VR4122_RTCINT_REG_W
157 #if defined VRGROUP_4181
158 #define RTCINT_REG_W VR4181_RTCINT_REG_W
162 #define RTCINT_TCLOCK (1<<3)
163 #define RTCINT_RTCLONG2 (1<<2)
164 #define RTCINT_RTCLONG1 (1<<1)
165 #define RTCINT_ELAPSED (1)
166 #define RTCINT_ALL (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED)
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