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power.h
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1 /* Copyright (c) 2006, 2007, 2008 Eric B. Weddington
2  Copyright (c) 2011 Frédéric Nadeau
3  All rights reserved.
4 
5  Redistribution and use in source and binary forms, with or without
6  modification, are permitted provided that the following conditions are met:
7 
8  * Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10  * Redistributions in binary form must reproduce the above copyright
11  notice, this list of conditions and the following disclaimer in
12  the documentation and/or other materials provided with the
13  distribution.
14  * Neither the name of the copyright holders nor the names of
15  contributors may be used to endorse or promote products derived
16  from this software without specific prior written permission.
17 
18  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  POSSIBILITY OF SUCH DAMAGE. */
29 
30 /* $Id$ */
31 
32 #ifndef _AVR_POWER_H_
33 #define _AVR_POWER_H_ 1
34 
35 #include <avr/io.h>
36 #include <stdint.h>
37 
38 /** \file */
39 /** \defgroup avr_power <avr/power.h>: Power Reduction Management
40 
41 \code #include <avr/power.h>\endcode
42 
43 Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
44 allow you to reduce power consumption by disabling or enabling various on-board
45 peripherals as needed. Some devices have the XTAL Divide Control Register
46 (XDIV) which offer similar functionality as System Clock Prescale
47 Register (CLKPR).
48 
49 There are many macros in this header file that provide an easy interface
50 to enable or disable on-board peripherals to reduce power. See the table below.
51 
52 \note Not all AVR devices have a Power Reduction Register (for example
53 the ATmega8). On those devices without a Power Reduction Register, the
54 power reduction macros are not available..
55 
56 \note Not all AVR devices contain the same peripherals (for example, the LCD
57 interface), or they will be named differently (for example, USART and
58 USART0). Please consult your device's datasheet, or the header file, to
59 find out which macros are applicable to your device.
60 
61 \note For device using the XTAL Divide Control Register (XDIV), when prescaler
62 is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
63 that Timer/Counter0 source shall be less than ¼th of peripheral clock.
64 Therefore, when using a typical 32.768 kHz crystal, one shall not scale
65 the clock below 131.072 kHz.
66 
67 */
68 
69 
70 /** \addtogroup avr_power
71 
72 \anchor avr_powermacros
73 <small>
74 <center>
75 <table border="3">
76  <tr>
77  <td width="10%"><strong>Power Macro</strong></td>
78  <td width="15%"><strong>Description</strong></td>
79  </tr>
80 
81  <tr>
82  <td>power_aca_disable()</td>
83  <td>Disable the Analog Comparator on PortA.</td>
84  </tr>
85 
86  <tr>
87  <td>power_aca_enable()</td>
88  <td>Enable the Analog Comparator on PortA.</td>
89  </tr>
90 
91  <tr>
92  <td>power_adc_enable()</td>
93  <td>Enable the Analog to Digital Converter module.</td>
94  </tr>
95 
96  <tr>
97  <td>power_adc_disable()</td>
98  <td>Disable the Analog to Digital Converter module.</td>
99  </tr>
100 
101  <tr>
102  <td>power_adca_disable()</td>
103  <td>Disable the Analog to Digital Converter module on PortA</td>
104  </tr>
105 
106  <tr>
107  <td>power_adca_enable()</td>
108  <td>Enable the Analog to Digital Converter module on PortA</td>
109  </tr>
110 
111  <tr>
112  <td>power_evsys_disable()</td>
113  <td>Disable the EVSYS module</td>
114  </tr>
115 
116  <tr>
117  <td>power_evsys_enable()</td>
118  <td>Enable the EVSYS module</td>
119  </tr>
120 
121  <tr>
122  <td>power_hiresc_disable()</td>
123  <td>Disable the HIRES module on PortC</td>
124  </tr>
125 
126  <tr>
127  <td>power_hiresc_enable()</td>
128  <td>Enable the HIRES module on PortC</td>
129  </tr>
130 
131  <tr>
132  <td>power_lcd_enable()</td>
133  <td>Enable the LCD module.</td>
134  </tr>
135 
136  <tr>
137  <td>power_lcd_disable().</td>
138  <td>Disable the LCD module.</td>
139  </tr>
140 
141  <tr>
142  <td>power_pga_enable()</td>
143  <td>Enable the Programmable Gain Amplifier module.</td>
144  </tr>
145 
146  <tr>
147  <td>power_pga_disable()</td>
148  <td>Disable the Programmable Gain Amplifier module.</td>
149  </tr>
150 
151  <tr>
152  <td>power_pscr_enable()</td>
153  <td>Enable the Reduced Power Stage Controller module.</td>
154  </tr>
155 
156  <tr>
157  <td>power_pscr_disable()</td>
158  <td>Disable the Reduced Power Stage Controller module.</td>
159  </tr>
160 
161  <tr>
162  <td>power_psc0_enable()</td>
163  <td>Enable the Power Stage Controller 0 module.</td>
164  </tr>
165 
166  <tr>
167  <td>power_psc0_disable()</td>
168  <td>Disable the Power Stage Controller 0 module.</td>
169  </tr>
170 
171  <tr>
172  <td>power_psc1_enable()</td>
173  <td>Enable the Power Stage Controller 1 module.</td>
174  </tr>
175 
176  <tr>
177  <td>power_psc1_disable()</td>
178  <td>Disable the Power Stage Controller 1 module.</td>
179  </tr>
180 
181  <tr>
182  <td>power_psc2_enable()</td>
183  <td>Enable the Power Stage Controller 2 module.</td>
184  </tr>
185 
186  <tr>
187  <td>power_psc2_disable()</td>
188  <td>Disable the Power Stage Controller 2 module.</td>
189  </tr>
190 
191  <tr>
192  <td>power_ram0_enable()</td>
193  <td>Enable the SRAM block 0 .</td>
194  </tr>
195 
196  <tr>
197  <td>power_ram0_disable()</td>
198  <td>Disable the SRAM block 0. </td>
199  </tr>
200 
201  <tr>
202  <td>power_ram1_enable()</td>
203  <td>Enable the SRAM block 1 .</td>
204  </tr>
205 
206  <tr>
207  <td>power_ram1_disable()</td>
208  <td>Disable the SRAM block 1. </td>
209  </tr>
210 
211  <tr>
212  <td>power_ram2_enable()</td>
213  <td>Enable the SRAM block 2 .</td>
214  </tr>
215 
216  <tr>
217  <td>power_ram2_disable()</td>
218  <td>Disable the SRAM block 2. </td>
219  </tr>
220 
221  <tr>
222  <td>power_ram3_enable()</td>
223  <td>Enable the SRAM block 3 .</td>
224  </tr>
225 
226  <tr>
227  <td>power_ram3_disable()</td>
228  <td>Disable the SRAM block 3. </td>
229  </tr>
230 
231  <tr>
232  <td>power_rtc_disable()</td>
233  <td>Disable the RTC module</td>
234  </tr>
235 
236  <tr>
237  <td>power_rtc_enable()</td>
238  <td>Enable the RTC module</td>
239  </tr>
240 
241  <tr>
242  <td>power_spi_enable()</td>
243  <td>Enable the Serial Peripheral Interface module.</td>
244  </tr>
245 
246  <tr>
247  <td>power_spi_disable()</td>
248  <td>Disable the Serial Peripheral Interface module.</td>
249  </tr>
250 
251  <tr>
252  <td>power_spic_disable()</td>
253  <td>Disable the SPI module on PortC</td>
254  </tr>
255 
256  <tr>
257  <td>power_spic_enable()</td>
258  <td>Enable the SPI module on PortC</td>
259  </tr>
260 
261  <tr>
262  <td>power_spid_disable()</td>
263  <td>Disable the SPI module on PortD</td>
264  </tr>
265 
266  <tr>
267  <td>power_spid_enable()</td>
268  <td>Enable the SPI module on PortD</td>
269  </tr>
270 
271  <tr>
272  <td>power_tc0c_disable()</td>
273  <td>Disable the TC0 module on PortC</td>
274  </tr>
275 
276  <tr>
277  <td>power_tc0c_enable()</td>
278  <td>Enable the TC0 module on PortC</td>
279  </tr>
280 
281  <tr>
282  <td>power_tc0d_disable()</td>
283  <td>Disable the TC0 module on PortD</td>
284  </tr>
285 
286  <tr>
287  <td>power_tc0d_enable()</td>
288  <td>Enable the TC0 module on PortD</td>
289  </tr>
290 
291  <tr>
292  <td>power_tc0e_disable()</td>
293  <td>Disable the TC0 module on PortE</td>
294  </tr>
295 
296  <tr>
297  <td>power_tc0e_enable()</td>
298  <td>Enable the TC0 module on PortE</td>
299  </tr>
300 
301  <tr>
302  <td>power_tc0f_disable()</td>
303  <td>Disable the TC0 module on PortF</td>
304  </tr>
305 
306  <tr>
307  <td>power_tc0f_enable()</td>
308  <td>Enable the TC0 module on PortF</td>
309  </tr>
310 
311  <tr>
312  <td>power_tc1c_disable()</td>
313  <td>Disable the TC1 module on PortC</td>
314  </tr>
315 
316  <tr>
317  <td>power_tc1c_enable()</td>
318  <td>Enable the TC1 module on PortC</td>
319  </tr>
320 
321  <tr>
322  <td>power_twic_disable()</td>
323  <td>Disable the Two Wire Interface module on PortC</td>
324  </tr>
325 
326  <tr>
327  <td>power_twic_enable()</td>
328  <td>Enable the Two Wire Interface module on PortC</td>
329  </tr>
330 
331  <tr>
332  <td>power_twie_disable()</td>
333  <td>Disable the Two Wire Interface module on PortE</td>
334  </tr>
335 
336  <tr>
337  <td>power_twie_enable()</td>
338  <td>Enable the Two Wire Interface module on PortE</td>
339  </tr>
340 
341  <tr>
342  <td>power_timer0_enable()</td>
343  <td>Enable the Timer 0 module.</td>
344  </tr>
345 
346  <tr>
347  <td>power_timer0_disable()</td>
348  <td>Disable the Timer 0 module.</td>
349  </tr>
350 
351  <tr>
352  <td>power_timer1_enable()</td>
353  <td>Enable the Timer 1 module.</td>
354  </tr>
355 
356  <tr>
357  <td>power_timer1_disable()</td>
358  <td>Disable the Timer 1 module.</td>
359  </tr>
360 
361  <tr>
362  <td>power_timer2_enable()</td>
363  <td>Enable the Timer 2 module.</td>
364  </tr>
365 
366  <tr>
367  <td>power_timer2_disable()</td>
368  <td>Disable the Timer 2 module.</td>
369  </tr>
370 
371  <tr>
372  <td>power_timer3_enable()</td>
373  <td>Enable the Timer 3 module.</td>
374  </tr>
375 
376  <tr>
377  <td>power_timer3_disable()</td>
378  <td>Disable the Timer 3 module.</td>
379  </tr>
380 
381  <tr>
382  <td>power_timer4_enable()</td>
383  <td>Enable the Timer 4 module.</td>
384  </tr>
385 
386  <tr>
387  <td>power_timer4_disable()</td>
388  <td>Disable the Timer 4 module.</td>
389  </tr>
390 
391  <tr>
392  <td>power_timer5_enable()</td>
393  <td>Enable the Timer 5 module.</td>
394  </tr>
395 
396  <tr>
397  <td>power_timer5_disable()</td>
398  <td>Disable the Timer 5 module.</td>
399  </tr>
400 
401  <tr>
402  <td>power_twi_enable()</td>
403  <td>Enable the Two Wire Interface module.</td>
404  </tr>
405 
406  <tr>
407  <td>power_twi_disable()</td>
408  <td>Disable the Two Wire Interface module.</td>
409  </tr>
410 
411  <tr>
412  <td>power_usart_enable()</td>
413  <td>Enable the USART module.</td>
414  </tr>
415 
416  <tr>
417  <td>power_usart_disable()</td>
418  <td>Disable the USART module.</td>
419  </tr>
420 
421  <tr>
422  <td>power_usart0_enable()</td>
423  <td>Enable the USART 0 module.</td>
424  </tr>
425 
426  <tr>
427  <td>power_usart0_disable()</td>
428  <td>Disable the USART 0 module.</td>
429  </tr>
430 
431  <tr>
432  <td>power_usart1_enable()</td>
433  <td>Enable the USART 1 module.</td>
434  </tr>
435 
436  <tr>
437  <td>power_usart1_disable()</td>
438  <td>Disable the USART 1 module.</td>
439  </tr>
440 
441  <tr>
442  <td>power_usart2_enable()</td>
443  <td>Enable the USART 2 module.</td>
444  </tr>
445 
446  <tr>
447  <td>power_usart2_disable()</td>
448  <td>Disable the USART 2 module.</td>
449  </tr>
450 
451  <tr>
452  <td>power_usart3_enable()</td>
453  <td>Enable the USART 3 module.</td>
454  </tr>
455 
456  <tr>
457  <td>power_usart3_disable()</td>
458  <td>Disable the USART 3 module.</td>
459  </tr>
460 
461  <tr>
462  <td>power_usartc0_disable()</td>
463  <td> Disable the USART0 module on PortC</td>
464  </tr>
465 
466  <tr>
467  <td>power_usartc0_enable()</td>
468  <td> Enable the USART0 module on PortC</td>
469  </tr>
470 
471  <tr>
472  <td>power_usartd0_disable()</td>
473  <td> Disable the USART0 module on PortD</td>
474  </tr>
475 
476  <tr>
477  <td>power_usartd0_enable()</td>
478  <td> Enable the USART0 module on PortD</td>
479  </tr>
480 
481  <tr>
482  <td>power_usarte0_disable()</td>
483  <td> Disable the USART0 module on PortE</td>
484  </tr>
485 
486  <tr>
487  <td>power_usarte0_enable()</td>
488  <td> Enable the USART0 module on PortE</td>
489  </tr>
490 
491  <tr>
492  <td>power_usartf0_disable()</td>
493  <td> Disable the USART0 module on PortF</td>
494  </tr>
495 
496  <tr>
497  <td>power_usartf0_enable()</td>
498  <td> Enable the USART0 module on PortF</td>
499  </tr>
500 
501  <tr>
502  <td>power_usb_enable()</td>
503  <td>Enable the USB module.</td>
504  </tr>
505 
506  <tr>
507  <td>power_usb_disable()</td>
508  <td>Disable the USB module.</td>
509  </tr>
510 
511  <tr>
512  <td>power_usi_enable()</td>
513  <td>Enable the Universal Serial Interface module.</td>
514  </tr>
515 
516  <tr>
517  <td>power_usi_disable()</td>
518  <td>Disable the Universal Serial Interface module.</td>
519  </tr>
520 
521  <tr>
522  <td>power_vadc_enable()</td>
523  <td>Enable the Voltage ADC module.</td>
524  </tr>
525 
526  <tr>
527  <td>power_vadc_disable()</td>
528  <td>Disable the Voltage ADC module.</td>
529  </tr>
530 
531  <tr>
532  <td>power_all_enable()</td>
533  <td>Enable all modules.</td>
534  </tr>
535 
536  <tr>
537  <td>power_all_disable()</td>
538  <td>Disable all modules.</td>
539  </tr>
540 </table>
541 </center>
542 </small>
543 
544 @} */
545 
546 #if defined(__AVR_HAVE_PRR_PRADC)
547 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
548 #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
549 #endif
550 
551 #if defined(__AVR_HAVE_PRR_PRCAN)
552 #define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN))
553 #define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN))
554 #endif
555 
556 #if defined(__AVR_HAVE_PRR_PRLCD)
557 #define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD))
558 #define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD))
559 #endif
560 
561 #if defined(__AVR_HAVE_PRR_PRLIN)
562 #define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN))
563 #define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN))
564 #endif
565 
566 #if defined(__AVR_HAVE_PRR_PRPSC)
567 #define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC))
568 #define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC))
569 #endif
570 
571 #if defined(__AVR_HAVE_PRR_PRPSC0)
572 #define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0))
573 #define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0))
574 #endif
575 
576 #if defined(__AVR_HAVE_PRR_PRPSC1)
577 #define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1))
578 #define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1))
579 #endif
580 
581 #if defined(__AVR_HAVE_PRR_PRPSC2)
582 #define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
583 #define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
584 #endif
585 
586 #if defined(__AVR_HAVE_PRR_PRSCR)
587 #define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR))
588 #define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR))
589 #endif
590 
591 #if defined(__AVR_HAVE_PRR_PRSPI)
592 #define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
593 #define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
594 #endif
595 
596 #if defined(__AVR_HAVE_PRR_PRTIM0)
597 #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
598 #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
599 #endif
600 
601 #if defined(__AVR_HAVE_PRR_PRTIM1)
602 #define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
603 #define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
604 #endif
605 
606 #if defined(__AVR_HAVE_PRR_PRTIM2)
607 #define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2))
608 #define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2))
609 #endif
610 
611 #if defined(__AVR_HAVE_PRR_PRTWI)
612 #define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
613 #define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
614 #endif
615 
616 #if defined(__AVR_HAVE_PRR_PRUSART)
617 #define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART))
618 #define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART))
619 #endif
620 
621 #if defined(__AVR_HAVE_PRR_PRUSART0)
622 #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
623 #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
624 #endif
625 
626 #if defined(__AVR_HAVE_PRR_PRUSART1)
627 #define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1))
628 #define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1))
629 #endif
630 
631 #if defined(__AVR_HAVE_PRR_PRUSI)
632 #define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
633 #define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
634 #endif
635 
636 #if defined(__AVR_HAVE_PRR0_PRADC)
637 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
638 #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
639 #endif
640 
641 #if defined(__AVR_HAVE_PRR0_PRC0)
642 #define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO))
643 #define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO))
644 #endif
645 
646 #if defined(__AVR_HAVE_PRR0_PRCRC)
647 #define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC))
648 #define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC))
649 #endif
650 
651 #if defined(__AVR_HAVE_PRR0_PRCU)
652 #define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU))
653 #define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU))
654 #endif
655 
656 #if defined(__AVR_HAVE_PRR0_PRDS)
657 #define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS))
658 #define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS))
659 #endif
660 
661 #if defined(__AVR_HAVE_PRR0_PRLFR)
662 #define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR))
663 #define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR))
664 #endif
665 
666 #if defined(__AVR_HAVE_PRR0_PRLIN)
667 #define power_lin_enable() (PRR0 &= (uint8_t)~(1 << PRLIN))
668 #define power_lin_disable() (PRR0 |= (uint8_t)(1 << PRLIN))
669 #endif
670 
671 #if defined(__AVR_HAVE_PRR0_PRPGA)
672 #define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA))
673 #define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA))
674 #endif
675 
676 #if defined(__AVR_HAVE_PRR0_PRRXDC)
677 #define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC))
678 #define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC))
679 #endif
680 
681 #if defined(__AVR_HAVE_PRR0_PRSPI)
682 #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
683 #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
684 #endif
685 
686 #if defined(__AVR_HAVE_PRR0_PRT0)
687 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRT0))
688 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRT0))
689 #endif
690 
691 #if defined(__AVR_HAVE_PRR0_PRTIM0)
692 #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
693 #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
694 #endif
695 
696 #if defined(__AVR_HAVE_PRR0_PRT1)
697 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1))
698 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1))
699 #endif
700 
701 #if defined(__AVR_HAVE_PRR0_PRTIM1)
702 #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
703 #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
704 #endif
705 
706 #if defined(__AVR_HAVE_PRR0_PRT2)
707 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2))
708 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2))
709 #endif
710 
711 #if defined(__AVR_HAVE_PRR0_PRTIM2)
712 #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
713 #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
714 #endif
715 
716 #if defined(__AVR_HAVE_PRR0_PRT3)
717 #define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3))
718 #define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3))
719 #endif
720 
721 #if defined(__AVR_HAVE_PRR0_PRTM)
722 #define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM))
723 #define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM))
724 #endif
725 
726 #if defined(__AVR_HAVE_PRR0_PRTWI)
727 #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
728 #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
729 #endif
730 
731 #if defined(__AVR_HAVE_PRR0_PRTXDC)
732 #define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC))
733 #define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC))
734 #endif
735 
736 #if defined(__AVR_HAVE_PRR0_PRUSART0)
737 #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
738 #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
739 #endif
740 
741 #if defined(__AVR_HAVE_PRR0_PRUSART1)
742 #define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1))
743 #define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1))
744 #endif
745 
746 #if defined(__AVR_HAVE_PRR0_PRVADC)
747 #define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC))
748 #define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC))
749 #endif
750 
751 #if defined(__AVR_HAVE_PRR0_PRVM)
752 #define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM))
753 #define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
754 #endif
755 
756 #if defined(__AVR_HAVE_PRR0_PRVRM)
757 #define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM))
758 #define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM))
759 #endif
760 
761 #if defined(__AVR_HAVE_PRR1_PRAES)
762 #define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES))
763 #define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES))
764 #endif
765 
766 #if defined(__AVR_HAVE_PRR1_PRCI)
767 #define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI))
768 #define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI))
769 #endif
770 
771 #if defined(__AVR_HAVE_PRR1_PRHSSPI)
772 #define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI))
773 #define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI))
774 #endif
775 
776 #if defined(__AVR_HAVE_PRR1_PRKB)
777 #define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB))
778 #define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB))
779 #endif
780 
781 #if defined(__AVR_HAVE_PRR1_PRLFR)
782 #define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR))
783 #define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR))
784 #endif
785 
786 #if defined(__AVR_HAVE_PRR1_PRSCI)
787 #define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI))
788 #define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI))
789 #endif
790 
791 #if defined(__AVR_HAVE_PRR1_PRT1)
792 #define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1))
793 #define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1))
794 #endif
795 
796 #if defined(__AVR_HAVE_PRR1_PRT2)
797 #define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2))
798 #define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2))
799 #endif
800 
801 #if defined(__AVR_HAVE_PRR1_PRT3)
802 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3))
803 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3))
804 #endif
805 
806 #if defined(__AVR_HAVE_PRR1_PRT4)
807 #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4))
808 #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4))
809 #endif
810 
811 #if defined(__AVR_HAVE_PRR1_PRT5)
812 #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5))
813 #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5))
814 #endif
815 
816 #if defined(__AVR_HAVE_PRR1_PRTIM3)
817 #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
818 #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
819 #endif
820 
821 #if defined(__AVR_HAVE_PRR1_PRTIM4)
822 #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
823 #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
824 #endif
825 
826 #if defined(__AVR_HAVE_PRR1_PRTIM5)
827 #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
828 #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
829 #endif
830 
831 #if defined(__AVR_HAVE_PRR1_PRTRX24)
832 #define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24))
833 #define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24))
834 #endif
835 
836 #if defined(__AVR_HAVE_PRR1_PRUSART1)
837 #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
838 #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
839 #endif
840 
841 #if defined(__AVR_HAVE_PRR1_PRUSART2)
842 #define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2))
843 #define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2))
844 #endif
845 
846 #if defined(__AVR_HAVE_PRR1_PRUSB)
847 #define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
848 #define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
849 #endif
850 
851 #if defined(__AVR_HAVE_PRR1_PRUSBH)
852 #define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH))
853 #define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH))
854 #endif
855 
856 #if defined(__AVR_HAVE_PRR2_PRDF)
857 #define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF))
858 #define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF))
859 #endif
860 
861 #if defined(__AVR_HAVE_PRR2_PRIDS)
862 #define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS))
863 #define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS))
864 #endif
865 
866 #if defined(__AVR_HAVE_PRR2_PRRAM0)
867 #define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0))
868 #define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0))
869 #endif
870 
871 #if defined(__AVR_HAVE_PRR2_PRRAM1)
872 #define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1))
873 #define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1))
874 #endif
875 
876 #if defined(__AVR_HAVE_PRR2_PRRAM2)
877 #define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2))
878 #define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2))
879 #endif
880 
881 #if defined(__AVR_HAVE_PRR2_PRRAM3)
882 #define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3))
883 #define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3))
884 #endif
885 
886 #if defined(__AVR_HAVE_PRR2_PRRS)
887 #define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS))
888 #define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS))
889 #endif
890 
891 #if defined(__AVR_HAVE_PRR2_PRSF)
892 #define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF))
893 #define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF))
894 #endif
895 
896 #if defined(__AVR_HAVE_PRR2_PRSSM)
897 #define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM))
898 #define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM))
899 #endif
900 
901 #if defined(__AVR_HAVE_PRR2_PRTM)
902 #define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM))
903 #define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM))
904 #endif
905 
906 #if defined(__AVR_HAVE_PRR2_PRXA)
907 #define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA))
908 #define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA))
909 #endif
910 
911 #if defined(__AVR_HAVE_PRR2_PRXB)
912 #define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB))
913 #define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB))
914 #endif
915 
916 #if defined(__AVR_HAVE_PRGEN_AES)
917 #define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
918 #define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
919 #endif
920 
921 #if defined(__AVR_HAVE_PRGEN_DMA)
922 #define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
923 #define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
924 #endif
925 
926 #if defined(__AVR_HAVE_PRGEN_EBI)
927 #define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
928 #define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm)
929 #endif
930 
931 #if defined(__AVR_HAVE_PRGEN_EDMA)
932 #define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm))
933 #define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm)
934 #endif
935 
936 #if defined(__AVR_HAVE_PRGEN_EVSYS)
937 #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
938 #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
939 #endif
940 
941 #if defined(__AVR_HAVE_PRGEN_LCD)
942 #define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm))
943 #define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm)
944 #endif
945 
946 #if defined(__AVR_HAVE_PRGEN_RTC)
947 #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
948 #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
949 #endif
950 
951 #if defined(__AVR_HAVE_PRGEN_USB)
952 #define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
953 #define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm))
954 #endif
955 
956 #if defined(__AVR_HAVE_PRGEN_XCL)
957 #define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm))
958 #define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm)
959 #endif
960 
961 #if defined(__AVR_HAVE_PRPA_AC)
962 #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
963 #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
964 #endif
965 
966 #if defined(__AVR_HAVE_PRPA_ADC)
967 #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
968 #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
969 #endif
970 
971 #if defined(__AVR_HAVE_PRPA_DAC)
972 #define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
973 #define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
974 #endif
975 
976 #if defined(__AVR_HAVE_PRPB_AC)
977 #define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
978 #define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
979 #endif
980 
981 #if defined(__AVR_HAVE_PRPB_ADC)
982 #define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
983 #define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
984 #endif
985 
986 #if defined(__AVR_HAVE_PRPB_DAC)
987 #define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
988 #define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm)
989 #endif
990 
991 #if defined(__AVR_HAVE_PRPC_HIRES)
992 #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
993 #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
994 #endif
995 
996 #if defined(__AVR_HAVE_PRPC_SPI)
997 #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
998 #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
999 #endif
1000 
1001 #if defined(__AVR_HAVE_PRPC_TC0)
1002 #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
1003 #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
1004 #endif
1005 
1006 #if defined(__AVR_HAVE_PRPC_TC1)
1007 #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
1008 #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
1009 #endif
1010 
1011 #if defined(__AVR_HAVE_PRPC_TC4)
1012 #define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm))
1013 #define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm)
1014 #endif
1015 
1016 #if defined(__AVR_HAVE_PRPC_TC5)
1017 #define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm))
1018 #define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm)
1019 #endif
1020 
1021 #if defined(__AVR_HAVE_PRPC_TWI)
1022 #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
1023 #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
1024 #endif
1025 
1026 #if defined(__AVR_HAVE_PRPC_USART0)
1027 #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
1028 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
1029 #endif
1030 
1031 #if defined(__AVR_HAVE_PRPC_USART1)
1032 #define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
1033 #define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
1034 #endif
1035 
1036 #if defined(__AVR_HAVE_PRPD_HIRES)
1037 #define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
1038 #define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm)
1039 #endif
1040 
1041 #if defined(__AVR_HAVE_PRPD_SPI)
1042 #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
1043 #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
1044 #endif
1045 
1046 #if defined(__AVR_HAVE_PRPD_TC0)
1047 #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
1048 #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
1049 #endif
1050 
1051 #if defined(__AVR_HAVE_PRPD_TC1)
1052 #define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
1053 #define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm)
1054 #endif
1055 
1056 #if defined(__AVR_HAVE_PRPD_TC5)
1057 #define power_tc5d_enable() (PR_PRPD &= (uint8_t)~(PR_TC5_bm))
1058 #define power_tc5d_disable() (PR_PRPD |= (uint8_t)PR_TC5_bm)
1059 #endif
1060 
1061 #if defined(__AVR_HAVE_PRPD_TWI)
1062 #define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
1063 #define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm)
1064 #endif
1065 
1066 #if defined(__AVR_HAVE_PRPD_USART0)
1067 #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
1068 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
1069 #endif
1070 
1071 #if defined(__AVR_HAVE_PRPD_USART1)
1072 #define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
1073 #define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
1074 #endif
1075 
1076 #if defined(__AVR_HAVE_PRPE_HIRES)
1077 #define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
1078 #define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm)
1079 #endif
1080 
1081 #if defined(__AVR_HAVE_PRPE_SPI)
1082 #define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
1083 #define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm)
1084 #endif
1085 
1086 #if defined(__AVR_HAVE_PRPE_TC0)
1087 #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1088 #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1089 #endif
1090 
1091 #if defined(__AVR_HAVE_PRPE_TC1)
1092 #define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
1093 #define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm)
1094 #endif
1095 
1096 #if defined(__AVR_HAVE_PRPE_TWI)
1097 #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
1098 #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
1099 #endif
1100 
1101 #if defined(__AVR_HAVE_PRPE_USART0)
1102 #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
1103 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
1104 #endif
1105 
1106 #if defined(__AVR_HAVE_PRPE_USART1)
1107 #define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
1108 #define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
1109 #endif
1110 
1111 #if defined(__AVR_HAVE_PRPF_HIRES)
1112 #define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
1113 #define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm)
1114 #endif
1115 
1116 #if defined(__AVR_HAVE_PRPF_SPI)
1117 #define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
1118 #define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm)
1119 #endif
1120 
1121 #if defined(__AVR_HAVE_PRPF_TC0)
1122 #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
1123 #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
1124 #endif
1125 
1126 #if defined(__AVR_HAVE_PRPF_TC1)
1127 #define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
1128 #define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm)
1129 #endif
1130 
1131 #if defined(__AVR_HAVE_PRPF_TWI)
1132 #define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
1133 #define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm)
1134 #endif
1135 
1136 #if defined(__AVR_HAVE_PRPF_USART0)
1137 #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
1138 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
1139 #endif
1140 
1141 #if defined(__AVR_HAVE_PRPF_USART1)
1142 #define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
1143 #define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
1144 #endif
1145 
1146 
1147 static __inline void
1148 __attribute__ ((__always_inline__))
1149 __power_all_enable()
1150 {
1151 #ifdef __AVR_HAVE_PRR
1152  PRR &= (uint8_t)~(__AVR_HAVE_PRR);
1153 #endif
1154 
1155 #ifdef __AVR_HAVE_PRR0
1156  PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0);
1157 #endif
1158 
1159 #ifdef __AVR_HAVE_PRR1
1160  PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1);
1161 #endif
1162 
1163 #ifdef __AVR_HAVE_PRR2
1164  PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2);
1165 #endif
1166 
1167 #ifdef __AVR_HAVE_PRGEN
1168  PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN);
1169 #endif
1170 
1171 #ifdef __AVR_HAVE_PRPA
1172  PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA);
1173 #endif
1174 
1175 #ifdef __AVR_HAVE_PRPB
1176  PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB);
1177 #endif
1178 
1179 #ifdef __AVR_HAVE_PRPC
1180  PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC);
1181 #endif
1182 
1183 #ifdef __AVR_HAVE_PRPD
1184  PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD);
1185 #endif
1186 
1187 #ifdef __AVR_HAVE_PRPE
1188  PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE);
1189 #endif
1190 
1191 #ifdef __AVR_HAVE_PRPF
1192  PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF);
1193 #endif
1194 }
1195 
1196 static __inline void
1197 __attribute__ ((__always_inline__))
1198 __power_all_disable()
1199 {
1200 #ifdef __AVR_HAVE_PRR
1201  PRR |= (uint8_t)(__AVR_HAVE_PRR);
1202 #endif
1203 
1204 #ifdef __AVR_HAVE_PRR0
1205  PRR0 |= (uint8_t)(__AVR_HAVE_PRR0);
1206 #endif
1207 
1208 #ifdef __AVR_HAVE_PRR1
1209  PRR1 |= (uint8_t)(__AVR_HAVE_PRR1);
1210 #endif
1211 
1212 #ifdef __AVR_HAVE_PRR2
1213  PRR2 |= (uint8_t)(__AVR_HAVE_PRR2);
1214 #endif
1215 
1216 #ifdef __AVR_HAVE_PRGEN
1217  PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN);
1218 #endif
1219 
1220 #ifdef __AVR_HAVE_PRPA
1221  PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA);
1222 #endif
1223 
1224 #ifdef __AVR_HAVE_PRPB
1225  PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB);
1226 #endif
1227 
1228 #ifdef __AVR_HAVE_PRPC
1229  PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC);
1230 #endif
1231 
1232 #ifdef __AVR_HAVE_PRPD
1233  PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD);
1234 #endif
1235 
1236 #ifdef __AVR_HAVE_PRPE
1237  PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE);
1238 #endif
1239 
1240 #ifdef __AVR_HAVE_PRPF
1241  PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF);
1242 #endif
1243 }
1244 
1245 #ifndef power_all_enable
1246 #define power_all_enable() __power_all_enable()
1247 #endif
1248 
1249 #ifndef power_all_disable
1250 #define power_all_disable() __power_all_disable()
1251 #endif
1252 
1253 #if defined(__AVR_AT90CAN32__) \
1254 || defined(__AVR_AT90CAN64__) \
1255 || defined(__AVR_AT90CAN128__) \
1256 || defined(__AVR_AT90PWM1__) \
1257 || defined(__AVR_AT90PWM2__) \
1258 || defined(__AVR_AT90PWM2B__) \
1259 || defined(__AVR_AT90PWM3__) \
1260 || defined(__AVR_AT90PWM3B__) \
1261 || defined(__AVR_AT90PWM81__) \
1262 || defined(__AVR_AT90PWM161__) \
1263 || defined(__AVR_AT90PWM216__) \
1264 || defined(__AVR_AT90PWM316__) \
1265 || defined(__AVR_AT90SCR100__) \
1266 || defined(__AVR_AT90USB646__) \
1267 || defined(__AVR_AT90USB647__) \
1268 || defined(__AVR_AT90USB82__) \
1269 || defined(__AVR_AT90USB1286__) \
1270 || defined(__AVR_AT90USB1287__) \
1271 || defined(__AVR_AT90USB162__) \
1272 || defined(__AVR_ATA5505__) \
1273 || defined(__AVR_ATA5272__) \
1274 || defined(__AVR_ATA6617C__) \
1275 || defined(__AVR_ATA664251__) \
1276 || defined(__AVR_ATmega1280__) \
1277 || defined(__AVR_ATmega1281__) \
1278 || defined(__AVR_ATmega1284__) \
1279 || defined(__AVR_ATmega128RFA1__) \
1280 || defined(__AVR_ATmega128RFR2__) \
1281 || defined(__AVR_ATmega1284RFR2__) \
1282 || defined(__AVR_ATmega1284P__) \
1283 || defined(__AVR_ATmega162__) \
1284 || defined(__AVR_ATmega164A__) \
1285 || defined(__AVR_ATmega164P__) \
1286 || defined(__AVR_ATmega164PA__) \
1287 || defined(__AVR_ATmega165__) \
1288 || defined(__AVR_ATmega165A__) \
1289 || defined(__AVR_ATmega165P__) \
1290 || defined(__AVR_ATmega165PA__) \
1291 || defined(__AVR_ATmega168__) \
1292 || defined(__AVR_ATmega168A__) \
1293 || defined(__AVR_ATmega168P__) \
1294 || defined(__AVR_ATmega168PA__) \
1295 || defined(__AVR_ATmega168PB__) \
1296 || defined(__AVR_ATmega169__) \
1297 || defined(__AVR_ATmega169A__) \
1298 || defined(__AVR_ATmega169P__) \
1299 || defined(__AVR_ATmega169PA__) \
1300 || defined(__AVR_ATmega16M1__) \
1301 || defined(__AVR_ATmega16U2__) \
1302 || defined(__AVR_ATmega324PA__) \
1303 || defined(__AVR_ATmega16U4__) \
1304 || defined(__AVR_ATmega2560__) \
1305 || defined(__AVR_ATmega2561__) \
1306 || defined(__AVR_ATmega256RFR2__) \
1307 || defined(__AVR_ATmega2564RFR2__) \
1308 || defined(__AVR_ATmega324A__) \
1309 || defined(__AVR_ATmega324P__) \
1310 || defined(__AVR_ATmega325__) \
1311 || defined(__AVR_ATmega325A__) \
1312 || defined(__AVR_ATmega325P__) \
1313 || defined(__AVR_ATmega325PA__) \
1314 || defined(__AVR_ATmega3250__) \
1315 || defined(__AVR_ATmega3250A__) \
1316 || defined(__AVR_ATmega3250P__) \
1317 || defined(__AVR_ATmega3250PA__) \
1318 || defined(__AVR_ATmega328__) \
1319 || defined(__AVR_ATmega328P__) \
1320 || defined(__AVR_ATmega329__) \
1321 || defined(__AVR_ATmega329A__) \
1322 || defined(__AVR_ATmega329P__) \
1323 || defined(__AVR_ATmega329PA__) \
1324 || defined(__AVR_ATmega3290__) \
1325 || defined(__AVR_ATmega3290A__) \
1326 || defined(__AVR_ATmega3290P__) \
1327 || defined(__AVR_ATmega3290PA__) \
1328 || defined(__AVR_ATmega32C1__) \
1329 || defined(__AVR_ATmega32M1__) \
1330 || defined(__AVR_ATmega32U2__) \
1331 || defined(__AVR_ATmega32U4__) \
1332 || defined(__AVR_ATmega32U6__) \
1333 || defined(__AVR_ATmega48__) \
1334 || defined(__AVR_ATmega48A__) \
1335 || defined(__AVR_ATmega48PA__) \
1336 || defined(__AVR_ATmega48PB__) \
1337 || defined(__AVR_ATmega48P__) \
1338 || defined(__AVR_ATmega640__) \
1339 || defined(__AVR_ATmega649P__) \
1340 || defined(__AVR_ATmega644__) \
1341 || defined(__AVR_ATmega644A__) \
1342 || defined(__AVR_ATmega644P__) \
1343 || defined(__AVR_ATmega644PA__) \
1344 || defined(__AVR_ATmega645__) \
1345 || defined(__AVR_ATmega645A__) \
1346 || defined(__AVR_ATmega645P__) \
1347 || defined(__AVR_ATmega6450__) \
1348 || defined(__AVR_ATmega6450A__) \
1349 || defined(__AVR_ATmega6450P__) \
1350 || defined(__AVR_ATmega649__) \
1351 || defined(__AVR_ATmega649A__) \
1352 || defined(__AVR_ATmega64M1__) \
1353 || defined(__AVR_ATmega64C1__) \
1354 || defined(__AVR_ATmega88A__) \
1355 || defined(__AVR_ATmega88PA__) \
1356 || defined(__AVR_ATmega88PB__) \
1357 || defined(__AVR_ATmega6490__) \
1358 || defined(__AVR_ATmega6490A__) \
1359 || defined(__AVR_ATmega6490P__) \
1360 || defined(__AVR_ATmega64RFR2__) \
1361 || defined(__AVR_ATmega644RFR2__) \
1362 || defined(__AVR_ATmega88__) \
1363 || defined(__AVR_ATmega88P__) \
1364 || defined(__AVR_ATmega8U2__) \
1365 || defined(__AVR_ATmega16U2__) \
1366 || defined(__AVR_ATmega32U2__) \
1367 || defined(__AVR_ATtiny48__) \
1368 || defined(__AVR_ATtiny88__) \
1369 || defined(__AVR_ATtiny87__) \
1370 || defined(__AVR_ATtiny167__) \
1371 || defined(__DOXYGEN__)
1372 
1373 
1374 /** \addtogroup avr_power
1375 
1376 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
1377 allows you to decrease the system clock frequency and the power consumption
1378 when the need for processing power is low.
1379 On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar
1380 functionality can be achieved through the XTAL Divide Control Register.
1381 Below are two macros and an enumerated type that can be used to
1382 interface to the Clock Prescale Register or
1383 XTAL Divide Control Register.
1384 
1385 \note Not all AVR devices have a clock prescaler. On those devices
1386 without a Clock Prescale Register or XTAL Divide Control Register, these
1387 macros are not available.
1388 */
1389 
1390 
1391 /** \addtogroup avr_power
1392 \code
1393 typedef enum
1394 {
1395  clock_div_1 = 0,
1396  clock_div_2 = 1,
1397  clock_div_4 = 2,
1398  clock_div_8 = 3,
1399  clock_div_16 = 4,
1400  clock_div_32 = 5,
1401  clock_div_64 = 6,
1402  clock_div_128 = 7,
1403  clock_div_256 = 8,
1404  clock_div_1_rc = 15, // ATmega128RFA1 only
1405 } clock_div_t;
1406 \endcode
1407 Clock prescaler setting enumerations for device using
1408 System Clock Prescale Register.
1409 
1410 \code
1411 typedef enum
1412 {
1413  clock_div_1 = 1,
1414  clock_div_2 = 2,
1415  clock_div_4 = 4,
1416  clock_div_8 = 8,
1417  clock_div_16 = 16,
1418  clock_div_32 = 32,
1419  clock_div_64 = 64,
1420  clock_div_128 = 128
1421 } clock_div_t;
1422 \endcode
1423 Clock prescaler setting enumerations for device using
1424 XTAL Divide Control Register.
1425 
1426 */
1427 typedef enum
1428 {
1429  clock_div_1 = 0,
1430  clock_div_2 = 1,
1431  clock_div_4 = 2,
1432  clock_div_8 = 3,
1433  clock_div_16 = 4,
1434  clock_div_32 = 5,
1435  clock_div_64 = 6,
1436  clock_div_128 = 7,
1437  clock_div_256 = 8
1438 #if defined(__AVR_ATmega128RFA1__) \
1439 || defined(__AVR_ATmega256RFR2__) \
1440 || defined(__AVR_ATmega2564RFR2__) \
1441 || defined(__AVR_ATmega128RFR2__) \
1442 || defined(__AVR_ATmega1284RFR2__) \
1443 || defined(__AVR_ATmega64RFR2__) \
1444 || defined(__AVR_ATmega644RFR2__)
1445  , clock_div_1_rc = 15
1446 #endif
1447 } clock_div_t;
1448 
1449 
1450 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1451 
1452 /** \addtogroup avr_power
1453 \code clock_prescale_set(x) \endcode
1454 
1455 Set the clock prescaler register select bits, selecting a system clock
1456 division setting. This function is inlined, even if compiler
1457 optimizations are disabled.
1458 
1459 The type of \c x is \c clock_div_t.
1460 
1461 \note For device with XTAL Divide Control Register (XDIV), \c x can actually range
1462 from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument.
1463 */
1464 void clock_prescale_set(clock_div_t __x)
1465 {
1466  uint8_t __tmp = _BV(CLKPCE);
1467  __asm__ __volatile__ (
1468  "in __tmp_reg__,__SREG__" "\n\t"
1469  "cli" "\n\t"
1470  "sts %1, %0" "\n\t"
1471  "sts %1, %2" "\n\t"
1472  "out __SREG__, __tmp_reg__"
1473  : /* no outputs */
1474  : "d" (__tmp),
1475  "M" (_SFR_MEM_ADDR(CLKPR)),
1476  "d" (__x)
1477  : "r0");
1478 }
1479 
1480 /** \addtogroup avr_power
1481 \code clock_prescale_get() \endcode
1482 Gets and returns the clock prescaler register setting. The return type is \c clock_div_t.
1483 
1484 \note For device with XTAL Divide Control Register (XDIV), return can actually
1485 range from 1 to 129. Care should be taken has the return value could differ from the
1486 typedef enum clock_div_t. This should only happen if clock_prescale_set was previously
1487 called with a value other than those defined by \c clock_div_t.
1488 */
1489 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1490 
1491 #elif defined(__AVR_ATmega16HVB__) \
1492 || defined(__AVR_ATmega16HVBREVB__) \
1493 || defined(__AVR_ATmega64HVE__) \
1494 || defined(__AVR_ATmega32HVB__) \
1495 || defined(__AVR_ATmega32HVBREVB__) \
1496 || defined(__AVR_ATmega64HVE2__)
1497 
1498 typedef enum
1499 {
1500  clock_div_1 = 0,
1501  clock_div_2 = 1,
1502  clock_div_4 = 2,
1503  clock_div_8 = 3
1504 } clock_div_t;
1505 
1506 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1507 
1508 void clock_prescale_set(clock_div_t __x)
1509 {
1510  uint8_t __tmp = _BV(CLKPCE);
1511  __asm__ __volatile__ (
1512  "in __tmp_reg__,__SREG__" "\n\t"
1513  "cli" "\n\t"
1514  "sts %1, %0" "\n\t"
1515  "sts %1, %2" "\n\t"
1516  "out __SREG__, __tmp_reg__"
1517  : /* no outputs */
1518  : "d" (__tmp),
1519  "M" (_SFR_MEM_ADDR(CLKPR)),
1520  "d" (__x)
1521  : "r0");
1522 }
1523 
1524 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
1525 
1526 #elif defined(__AVR_ATA5790__) \
1527 || defined (__AVR_ATA5790N__) \
1528 || defined (__AVR_ATA5791__) \
1529 || defined (__AVR_ATA5795__)
1530 
1531 typedef enum
1532 {
1533  clock_div_1 = 0,
1534  clock_div_2 = 1,
1535  clock_div_4 = 2,
1536  clock_div_8 = 3,
1537  clock_div_16 = 4,
1538  clock_div_32 = 5,
1539  clock_div_64 = 6,
1540  clock_div_128 = 7,
1541 } clock_div_t;
1542 
1543 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1544 
1545 void system_clock_prescale_set(clock_div_t __x)
1546 {
1547  uint8_t __tmp = _BV(CLKPCE);
1548  __asm__ __volatile__ (
1549  "in __tmp_reg__,__SREG__" "\n\t"
1550  "cli" "\n\t"
1551  "out %1, %0" "\n\t"
1552  "out %1, %2" "\n\t"
1553  "out __SREG__, __tmp_reg__"
1554  : /* no outputs */
1555  : "d" (__tmp),
1556  "I" (_SFR_IO_ADDR(CLKPR)),
1557  "d" (__x)
1558  : "r0");
1559 }
1560 
1561 #define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1562 
1563 typedef enum
1564 {
1565  timer_clock_div_reset = 0,
1566  timer_clock_div_1 = 1,
1567  timer_clock_div_2 = 2,
1568  timer_clock_div_4 = 3,
1569  timer_clock_div_8 = 4,
1570  timer_clock_div_16 = 5,
1571  timer_clock_div_32 = 6,
1572  timer_clock_div_64 = 7
1573 } timer_clock_div_t;
1574 
1575 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
1576 
1577 void timer_clock_prescale_set(timer_clock_div_t __x)
1578 {
1579  uint8_t __t;
1580  __asm__ __volatile__ (
1581  "in __tmp_reg__,__SREG__" "\n\t"
1582  "cli" "\n\t"
1583  "in %[temp],%[clkpr]" "\n\t"
1584  "out %[clkpr],%[enable]" "\n\t"
1585  "andi %[temp],%[not_CLTPS]" "\n\t"
1586  "or %[temp], %[set_value]" "\n\t"
1587  "out %[clkpr],%[temp]" "\n\t"
1588  "sei" "\n\t"
1589  "out __SREG__,__tmp_reg__" "\n\t"
1590  : /* no outputs */
1591  : [temp] "r" (__t),
1592  [clkpr] "I" (_SFR_IO_ADDR(CLKPR)),
1593  [enable] "r" (_BV(CLKPCE)),
1594  [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1595  [set_value] "r" ((__x & 7) << 3)
1596  : "r0");
1597 }
1598 
1599 #define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1600 
1601 #elif defined(__AVR_ATA6285__) \
1602 || defined(__AVR_ATA6286__) \
1603 || defined(__AVR_ATA6289__) \
1604 || defined(__AVR_ATA5702M322__) \
1605 || defined(__AVR_ATA5782__) \
1606 || defined(__AVR_ATA8210__) \
1607 || defined(__AVR_ATA5831__) \
1608 || defined(__AVR_ATA8510__)
1609 
1610 typedef enum
1611 {
1612  clock_div_1 = 0,
1613  clock_div_2 = 1,
1614  clock_div_4 = 2,
1615  clock_div_8 = 3,
1616  clock_div_16 = 4,
1617  clock_div_32 = 5,
1618  clock_div_64 = 6,
1619  clock_div_128 = 7
1620 } clock_div_t;
1621 
1622 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1623 
1624 void system_clock_prescale_set(clock_div_t __x)
1625 {
1626  uint8_t __t;
1627  __asm__ __volatile__ (
1628  "in __tmp_reg__,__SREG__" "\n\t"
1629  "cli" "\n\t"
1630  "in %[temp],%[clpr]" "\n\t"
1631  "out %[clpr],%[enable]" "\n\t"
1632  "andi %[temp],%[not_CLKPS]" "\n\t"
1633  "or %[temp], %[set_value]" "\n\t"
1634  "out %[clpr],%[temp]" "\n\t"
1635  "sei" "\n\t"
1636  "out __SREG__,__tmp_reg__" "\n\t"
1637  : /* no outputs */
1638  : [temp] "r" (__t),
1639 #if defined(__AVR_ATA6286__) \
1640 || defined(__AVR_ATA6285__) \
1641 || defined(__AVR_ATA6289__)
1642  [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1643 #elif defined(__AVR_ATA5831__) \
1644 || defined(__AVR_ATA8510__) \
1645 || defined(__AVR_ATA5702M322__) \
1646 || defined(__AVR_ATA5782__) \
1647 || defined(__AVR_ATA8210__)
1648  [clpr] "I" (_SFR_IO_ADDR(CLPR)),
1649 #endif
1650  [enable] "r" _BV(CLPCE),
1651  [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
1652  [set_value] "r" (__x & 7)
1653  : "r0");
1654 }
1655 
1656 #if defined(__AVR_ATA6286__) \
1657 || defined(__AVR_ATA6285__) \
1658 || defined(__AVR_ATA6289__)
1659 
1660  #define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1661 
1662 #elif defined(__AVR_ATA5831__) \
1663 || defined(__AVR_ATA8510__) \
1664 || defined(__AVR_ATA5702M322__) \
1665 || defined(__AVR_ATA5782__) \
1666 || defined(__AVR_ATA8210__)
1667 
1668  #define system_clock_prescale_get() (clock_div_t)(CLPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1669 
1670 #endif
1671 
1672 typedef enum
1673 {
1674  timer_clock_div_reset = 0,
1675  timer_clock_div_1 = 1,
1676  timer_clock_div_2 = 2,
1677  timer_clock_div_4 = 3,
1678  timer_clock_div_8 = 4,
1679  timer_clock_div_16 = 5,
1680  timer_clock_div_32 = 6,
1681  timer_clock_div_64 = 7
1682 } timer_clock_div_t;
1683 
1684 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
1685 
1686 void timer_clock_prescale_set(timer_clock_div_t __x)
1687 {
1688  uint8_t __t;
1689  __asm__ __volatile__ (
1690  "in __tmp_reg__,__SREG__" "\n\t"
1691  "cli" "\n\t"
1692  "in %[temp],%[clpr]" "\n\t"
1693  "out %[clpr],%[enable]" "\n\t"
1694  "andi %[temp],%[not_CLTPS]" "\n\t"
1695  "or %[temp], %[set_value]" "\n\t"
1696  "out %[clpr],%[temp]" "\n\t"
1697  "sei" "\n\t"
1698  "out __SREG__,__tmp_reg__" "\n\t"
1699  : /* no outputs */
1700  : [temp] "r" (__t),
1701 #if defined(__AVR_ATA6286__) \
1702 || defined(__AVR_ATA6285__) \
1703 || defined(__AVR_ATA6289__)
1704  [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1705 #elif defined(__AVR_ATA5831__) \
1706 || defined(__AVR_ATA8510__) \
1707 || defined(__AVR_ATA5702M322__) \
1708 || defined(__AVR_ATA5782__) \
1709 || defined(__AVR_ATA8210__)
1710  [clpr] "I" (_SFR_IO_ADDR(CLPR)),
1711 #endif
1712  [enable] "r" (_BV(CLPCE)),
1713  [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1714  [set_value] "r" ((__x & 7) << 3)
1715  : "r0");
1716 }
1717 
1718 #if defined(__AVR_ATA6286__) \
1719 || defined(__AVR_ATA6285__) \
1720 || defined(__AVR_ATA6289__)
1721 
1722  #define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1723 
1724 #elif defined(__AVR_ATA5831__) \
1725 || defined(__AVR_ATA8510__) \
1726 || defined(__AVR_ATA5702M322__) \
1727 || defined(__AVR_ATA5782__) \
1728 || defined(__AVR_ATA8210__)
1729 
1730  #define timer_clock_prescale_get() (timer_clock_div_t)(CLPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1731 #endif
1732 
1733 #elif defined(__AVR_ATtiny24__) \
1734 || defined(__AVR_ATtiny24A__) \
1735 || defined(__AVR_ATtiny44__) \
1736 || defined(__AVR_ATtiny44A__) \
1737 || defined(__AVR_ATtiny84__) \
1738 || defined(__AVR_ATtiny84A__) \
1739 || defined(__AVR_ATtiny25__) \
1740 || defined(__AVR_ATtiny45__) \
1741 || defined(__AVR_ATtiny85__) \
1742 || defined(__AVR_ATtiny261A__) \
1743 || defined(__AVR_ATtiny261__) \
1744 || defined(__AVR_ATtiny461__) \
1745 || defined(__AVR_ATtiny461A__) \
1746 || defined(__AVR_ATtiny861__) \
1747 || defined(__AVR_ATtiny861A__) \
1748 || defined(__AVR_ATtiny2313__) \
1749 || defined(__AVR_ATtiny2313A__) \
1750 || defined(__AVR_ATtiny4313__) \
1751 || defined(__AVR_ATtiny13__) \
1752 || defined(__AVR_ATtiny13A__) \
1753 || defined(__AVR_ATtiny43U__) \
1754 
1755 typedef enum
1756 {
1757  clock_div_1 = 0,
1758  clock_div_2 = 1,
1759  clock_div_4 = 2,
1760  clock_div_8 = 3,
1761  clock_div_16 = 4,
1762  clock_div_32 = 5,
1763  clock_div_64 = 6,
1764  clock_div_128 = 7,
1765  clock_div_256 = 8
1766 } clock_div_t;
1767 
1768 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1769 
1770 void clock_prescale_set(clock_div_t __x)
1771 {
1772  uint8_t __tmp = _BV(CLKPCE);
1773  __asm__ __volatile__ (
1774  "in __tmp_reg__,__SREG__" "\n\t"
1775  "cli" "\n\t"
1776  "out %1, %0" "\n\t"
1777  "out %1, %2" "\n\t"
1778  "out __SREG__, __tmp_reg__"
1779  : /* no outputs */
1780  : "d" (__tmp),
1781  "I" (_SFR_IO_ADDR(CLKPR)),
1782  "d" (__x)
1783  : "r0");
1784 }
1785 
1786 
1787 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1788 
1789 #elif defined(__AVR_ATtiny441__) \
1790 || defined(__AVR_ATtiny841__)
1791 
1792 typedef enum
1793 {
1794  clock_div_1 = 0,
1795  clock_div_2 = 1,
1796  clock_div_4 = 2,
1797  clock_div_8 = 3,
1798  clock_div_16 = 4,
1799  clock_div_32 = 5,
1800  clock_div_64 = 6,
1801  clock_div_128 = 7,
1802  clock_div_256 = 8
1803 } clock_div_t;
1804 
1805 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1806 
1807 void clock_prescale_set(clock_div_t __x)
1808 {
1809 
1810  __asm__ __volatile__ (
1811  "in __tmp_reg__,__SREG__" "\n\t"
1812  "cli" "\n\t"
1813  "sts %2, %3" "\n\t"
1814  "sts %1, %0" "\n\t"
1815  "out __SREG__, __tmp_reg__"
1816  : /* no outputs */
1817  : "d" (__x),
1818  "M" (_SFR_MEM_ADDR(CLKPR)),
1819  "M" (_SFR_MEM_ADDR(CCP)),
1820  "r" ((uint8_t)0xD8)
1821  : "r0");
1822 }
1823 
1824 
1825 #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1826 
1827 #elif defined(__AVR_ATtiny4__) \
1828 || defined(__AVR_ATtiny5__) \
1829 || defined(__AVR_ATtiny9__) \
1830 || defined(__AVR_ATtiny10__) \
1831 || defined(__AVR_ATtiny20__) \
1832 || defined(__AVR_ATtiny40__) \
1833 
1834 typedef enum
1835 {
1836  clock_div_1 = 0,
1837  clock_div_2 = 1,
1838  clock_div_4 = 2,
1839  clock_div_8 = 3,
1840  clock_div_16 = 4,
1841  clock_div_32 = 5,
1842  clock_div_64 = 6,
1843  clock_div_128 = 7,
1844  clock_div_256 = 8
1845 } clock_div_t;
1846 
1847 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1848 
1849 void clock_prescale_set(clock_div_t __x)
1850 {
1851  uint8_t __tmp = 0xD8;
1852  __asm__ __volatile__ (
1853  "in __tmp_reg__,__SREG__" "\n\t"
1854  "cli" "\n\t"
1855  "out %1, %0" "\n\t"
1856  "out %2, %3" "\n\t"
1857  "out __SREG__, __tmp_reg__"
1858  : /* no outputs */
1859  : "d" (__tmp),
1860  "I" (_SFR_IO_ADDR(CCP)),
1861  "I" (_SFR_IO_ADDR(CLKPSR)),
1862  "d" (__x)
1863  : "r16");
1864 }
1865 
1866 #define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1867 
1868 #elif defined(__AVR_ATmega64__) \
1869 || defined(__AVR_ATmega103__) \
1870 || defined(__AVR_ATmega128__)
1871 
1872 //Enum is declared for code compatibility
1873 typedef enum
1874 {
1875  clock_div_1 = 1,
1876  clock_div_2 = 2,
1877  clock_div_4 = 4,
1878  clock_div_8 = 8,
1879  clock_div_16 = 16,
1880  clock_div_32 = 32,
1881  clock_div_64 = 64,
1882  clock_div_128 = 128
1883 } clock_div_t;
1884 
1885 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1886 
1887 void clock_prescale_set(clock_div_t __x)
1888 {
1889  if((__x <= 0) || (__x > 129))
1890  {
1891  return;//Invalid value.
1892  }
1893  else
1894  {
1895  uint8_t __tmp = 0;
1896  //Algo explained:
1897  //1 - Clear XDIV in order for it to accept a new value (actually only
1898  // XDIVEN need to be cleared, but clearing XDIV is faster than
1899  // read-modify-write since we will rewrite XDIV later anyway)
1900  //2 - wait 8 clock cycle for stability, see datasheet erreta
1901  //3 - Exist if requested prescaller is 1
1902  //4 - Calculate XDIV6..0 value = 129 - __x
1903  //5 - Set XDIVEN bit in calculated value
1904  //6 - write XDIV with calculated value
1905  //7 - wait 8 clock cycle for stability, see datasheet erreta
1906  __asm__ __volatile__ (
1907  "in __tmp_reg__,__SREG__" "\n\t"
1908  "cli" "\n\t"
1909  "out %1, __zero_reg__" "\n\t"
1910  "nop" "\n\t"
1911  "nop" "\n\t"
1912  "nop" "\n\t"
1913  "nop" "\n\t"
1914  "nop" "\n\t"
1915  "nop" "\n\t"
1916  "nop" "\n\t"
1917  "nop" "\n\t"
1918  "cpi %0, 0x01" "\n\t"
1919  "breq L_%=" "\n\t"
1920  "ldi %2, 0x81" "\n\t" //129
1921  "sub %2, %0" "\n\t"
1922  "ori %2, 0x80" "\n\t" //128
1923  "out %1, %2" "\n\t"
1924  "nop" "\n\t"
1925  "nop" "\n\t"
1926  "nop" "\n\t"
1927  "nop" "\n\t"
1928  "nop" "\n\t"
1929  "nop" "\n\t"
1930  "nop" "\n\t"
1931  "nop" "\n\t"
1932  "L_%=: " "out __SREG__, __tmp_reg__"
1933  : /* no outputs */
1934  :"d" (__x),
1935  "I" (_SFR_IO_ADDR(XDIV)),
1936  "d" (__tmp)
1937  : "r0");
1938  }
1939 }
1940 
1941 static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__));
1942 
1943 clock_div_t clock_prescale_get(void)
1944 {
1945  if(bit_is_clear(XDIV, XDIVEN))
1946  {
1947  return 1;
1948  }
1949  else
1950  {
1951  return (clock_div_t)(129 - (XDIV & 0x7F));
1952  }
1953 }
1954 
1955 #endif
1956 
1957 #endif /* _AVR_POWER_H_ */
static __inline void __attribute__((__always_inline__)) __power_all_enable()
Definition: power.h:1148
#define bit_is_clear(sfr, bit)
Definition: sfr_defs.h:245
unsigned char uint8_t
Definition: stdint.h:79
#define _BV(bit)
Definition: sfr_defs.h:208

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